參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標量微處理器)
中文描述: 超標量微處理器(超標量微處理器)
文件頁數(shù): 86/172頁
文件大?。?/td> 1142K
代理商: LR4500
5-16
Bus Interface Descriptions
SCBERRn
Bus Error
The Lbus master device asserts SCBERRn to terminate
the current transaction when a bus error occurs. If
SCBRDYn, or the bus retry signal, SCBRTYn, is asserted
at the same time as SCBERRn, SCBERRn has higher
priority. SCBERRn is reported to the CP0, which in turn
generates an exception.
Input to Shell from SCLC
SCBPWAn
Bus In-Page Write Accept
Input to Shell from
DRAMC
The DRAMC asserts SCBPWAn to indicate that it
accepts in-page write transactions. The CW4011
samples the signal on the rising edge of the clock that
synchronizes SCBRDYn. If the CW4011 has not asserted
SCTPWn, asserting or deasserting SCBPWAn has no
significance.
SCBRDYn
Bus Ready
The SCLC asserts SCBRDYn when the current
transaction is terminated, indicating that the SCbus is
available. The signal remains active (LOW) until the next
transaction starts. The SCLC deasserts the signal to
indicate that the SCbus is not available. The SCLC
receives a bus-ready signal, DRRDYn, from the DRAMC
(
page 5-19
), merges DRRDYn with the SCLC bus ready
signal, and drives SCBRDYn, which is output to the
CW4011 shell.
Input to Shell from SCLC
SCBRTYn
Bus Retry
The Lbus master device asserts SCBRTYn when the
current transaction has been terminated unsuccessfully
and must be retried later. The control state goes back to
the idle state, then all bus requests are arbitrated again.
If there are no higher priority requests and the Lbus
master has asserted SCTSEn, there is one idle state
between the first transaction and a retry transaction. If
SCBRDYn and SCBRTYn are asserted at the same time,
SCBRTYn has the higher priority.
Input to Shell from SCLC
SCDp[63:0]
Data Bus
Bidirectional between Shell, SCLC,
and DRAMC
SCDp[63:0] are the data bus signals. They are output
from the CW4011 shell for data read/write operations and
for data write back to the D-cache. They are input to the
shell for data read and instruction fetch transactions. The
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