參數(shù)資料
型號: M37920FCCGP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù): 113/158頁
文件大?。?/td> 1261K
代理商: M37920FCCGP
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
58
Fig. 54 Bit configuration of UARTi transmit/receive control register
/LSB
MSB
TX
EPTY
76543210
R/C
CS1
CS0
BRG count source select bits
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
CTS/RTS function select bit (Note 1)
0 : CTS function is selected.
1 : RTS function is selected.
Transmit register empty flag
0 : Data is present in the transmit register. (Transmission is in progress.)
1 : No data is present in the transmit register. (Transmission is completed.)
CTS/RTS enable bit (Note 2)
0 : CTS, RTS function is enabled.
1 : CTS, RTS function is disabled.
UART receive interrupt mode select bit
0 : Reception interrupt
1 : Reception error interrupt
CLK polarity select bit (This bit is used in the clock synchronous serial I/O mode.) (Note 3)
0 : At the falling edge of a transfer clock, transmit data is output;
at the rising edge, receive data is input.
When not in transfer, pin CLK’s level is “H”.
1 : At the rising edge of a transfer clock, transmit data is output;
at the falling edge, receive data is input.
When not in transfer, pin CLK’s level is “L”.
Transfer format select bit (This bit is used in the clock synchronous serial I/O mode.) (Note 3)
0 : LSB (Least Significant Bit) first
1 : MSB (Most Significant Bit) first
76543210
RE
RI
OER
FER
PER
SUM
TI
TE
Transmit enable bit
Transmit buffer empty flag
Receive enable bit
Receive complete flag
Overrun error flag
Framing error flag (Note 4)
Parity error flag (Note 4)
Error sum flag (Note 4)
UART0 transmit/receive control register 0
UART1 transmit/receive control register 0
Address
34 16
3C16
UART0 transmit/receive control register 1
UART1 transmit/receive control register 1
Address
3516
3D16
CPL
Notes 1: Valid when the CTS/RTS enable bit = “0”.
2: Fix this bit to “1” in UART1 transmit/receive control register 0. (UART1 is not equipped with the CTS/RTS function.)
3: Fix this bit to “0” in UART mode or when serial I/O is invalid.
4: Valid in UART mode.
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