參數(shù)資料
型號: M37920FCCGP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù): 86/158頁
文件大?。?/td> 1261K
代理商: M37920FCCGP
33
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
7
6
543
2
1
0
CS0 control register L
External data bus width select bit
0 : 16-bit width
1 : 8-bit width
RDY control bit (Note 2)
0 : RDY control is valid.
1 : RDY control is invalid.
Area CS0 wait number select bits
0 0 : 0 wait
0 1 : 1 wait
1 0 : 2 wait
1 1 : ALE expansion wait (Note 1)
Address
8016
Burst ROM access select bit (Note 3)
0 : Normal access
1 : Burst ROM access
Recovery cycle insert select bit
0 : No recovery cycle is inserted at access to area CS0.
1 : Recovery cycle is inserted at access to area CS0.
CS0 output select bit
0 : CS0 output is disabled. (P90 functions as a programmble I/O port pin.)
1 : CS0 output is enabled. (P90 functions as pin CS0.)
Notes 1: When the burst ROM access is specified (bit 5= 1), be sure not to select “112” (ALE expansion wait).
2: This bit is valid when the RDY input select bit (bit 2 at address 5F16) = “1”.
3: While VCC level voltage is applied to pin BYTE, the normal access is selected regardless of this bit’s contents.
7
6
543
2
1
0
CS1 control register L
CS2 control register L
CS3 control register L
External data bus width select bit
0 : 16-bit width
1 : 8-bit width (Note 2)
RDY control bit (Note 3)
0 : RDY control is valid.
1 : RDY control is invalid.
Area CSj wait number select bits (j = 1 to 3)
0 0 : 0 wait
0 1 : 1 wait
1 0 : 2 wait
1 1 : ALE expansion wait (Note 1)
DRAM space select bit
0 : Except DRAM space
1 : DRAM space
Address
8216
8416
8616
Burst ROM access select bit (Note 4)
0 : Normal access
1 : Burst ROM access
Recovery cycle insert select bit (Note 5)
0 : No recovery cycle is inserted at access to area CSj.
1 : Recovery cycle is inserted at access to area CSj.
CSj output select bit (j = 1 to 3)
0 : CSj output is disabled. (P9j functions as programmable I/O port pins.)
1 : CSj output is enabled. (P9j functions as pin CSj.)
Notes 1: When the DRAM space is specified (bit 4 = 1), fix these bits to “012” (1 wait). Also, when the burst ROM access is
specified (bit 5 = 1), be sure not to select “112” (ALE expansion wait).
2: While VCC level voltage is applied to pin BYTE, this bit is fixed to “1” (8-bit width).
3: This bit is valid when the RDY input select bit (bit 2 at address 5F16) = “1”. Also, when DRAM space is specified
(bit 4 = 1), the RDY control is invalid regardless of this bit’s contets.
4: When only the external data bus width select bit (bit 2) = “1” or while VCC level voltage is applied to pin BYTE, the
normal access is selected regardless of this bit’s contents.
5: When the DRAM space is specified (bit 4 = 1), fix this bit to “0” (no recovery cycle).
“0” at read.
Fig. 15 Bit configuration of CS0/CS1/CS2/CS3 control register Ls
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