參數(shù)資料
型號： M37920FCCGP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 81/158頁
文件大?。?/td> 1261K
代理商： M37920FCCGP
29
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
Microprocessor mode
VCC level voltage is applied
10
SFR area
Internal RAM area
External memory area
Low-order address (A0 to A7) is output.
Middle-order address (A8 to A15) is output.
Multiplexed address (MA0 to MA7) is
output (Note 3)
High-order address (A16 to A23) is output.
Multiplexed address (MA8 to MA11) is
output (Note 3)
Low-order data (D0 to D7, data at even-
numbered address) is input/output.
Low-order data (D0 to D7, data at even-/
odd-numbered address) is input/output.
Low-order data (D0 to D7, data at odd-
numbered address) is input/output.
I/O port pins P20 to P27
Ready signal RDY is input.
I/O port pin P30 (Note 5)
Read signal RD is output
Write signal BLW (write to even-num-
bered address) is output.
Write signal BLW (write to even-/odd-
numbered address) is output.
Write signal BHW (write to odd-num-
bered address) is output.
I/O port pin P33
Memory expansion mode
VSS level voltage is applied
01
SFR area
Internal RAM area
Internal ROM area
External memory area
Low-order address (A0 to A7) is output.
Middle-order address (A8 to A15) is output.
Multiplexed address (MA0 to MA7) is output
(Note 3)
High-order address (A16 to A23) is output.
Multiplexed address (MA8 to MA11) is out-
put (Note 3)
Low-order data (D0 to D7, data at even-
numbered address) is input/output.
Low-order data (D0 to D7, data at even-/
odd-numbered address) is input/output.
Low-order data (D0 to D7, data at odd-num-
bered address) is input/output.
I/O port pins P20 to P27
I/O port pin P30
Ready signal RDY is input (Note 5).
Read signal RD is output.
Write signal BLW (write to even-numbered
address) is output.
Write signal BLW (write to even-/odd-num-
bered address) is output.
Write signal BHW (write to odd-numbered
address) is output.
I/O port pin P33
Table 10. Relationship between processor modes, memory area, and port function
Mode
(Note 1)
Single-chip mode
VSS level voltage is applied
00
SFR area
Internal RAM area
Internal ROM area
(Do not access.)
I/O port pins P100 to P107
I/O port pins P110 to P117
I/O port pins P00 to P07
I/O port pins P10 to P17
I/O port pins P20 to P27
I/O port pin P30
I/O port pin P31
I/O port pin P32
I/O port pin P33
Memory
area
Port pins P100 to P107
Port pins P110 to P117
Port pins P00 to P07
Port pins
P10 to P17
External data bus
width = 16 bits
External data bus
width = 8 bits
External data bus
width = 8 bits
Port pins
P20 to P27
Port pin P30
Port pin P31
External data bus
width = 16 bits
External data bus
width = 8 bits
External data bus
width = 16 bits
Port pin
P32
Port pin
P33
External data bus
width = 8 bits
Pin MD0
Processor mode
bits (Note 2)
SFR area
Internal RAM area
Internal ROM area
Other area
External data bus
width = 16 bits
Notes 1: For details of the processor mode setting, see Table 9.
2: Processor mode bits = bits 1 and 0 of the processor mode register 0 (address 5E16).
3: While DRAM space is accessed, the multiplexed address is output.
4: In the memory expansion mode, by the corresponding select bits of the processor mode register 0 and 1 (addresses 5E16, 5F16), port pins P30, P40 to
P43 can operate as pins for RDY input, ALE output,
φ1 output, HLDA output, HOLD input, respectively.
In the microprocessor mode, by the above select bits, the above pins (RDY, ALE,
φ1, HLDA, HOLD) can operate as port pins P30, P40 to P43, respec-
tively.
5: In the memory expansion mode, port pin P90 can operate as the CS0 output pin by the CS0 output select bit of the CS0 control register L (bit 7 at address 8016).
6: In the memory expansion and microprocessor modes, port pins P91 to P93 can operate as the CS1/CS2/CS3 output pins by the CSi output select bits (i =
1 to 3) (bit 7s at addresses 8216, 8416, 8616).
I/O port pin P40
I/O port pin P41
Clock
φ1 is output (Note 4).
I/O port pin P42
I/O port pin P43
I/O port pin P90
I/O port pins P91 to P93
Port pin P40
Port pin P41
Port pin P42
Port pin P43
Port pin P90
Port pins P91 to P93
I/O port pin P40
Address latch enable signal ALE is output (Note 4).
I/O port pin P41
Clock
φ1 is output (Note 4).
I/O port pin P42
Hold acknowledge signa HLDA is output (Note 4).
I/O port pin P43
Hold request signal HOLD is input (Note 4).
I/O port pin P90
Chip select signal CS0 is output (Note 5).
I/O port pins P91 to P93
Chip select signals CS1 to CS3 are output (Note 6).
Address latch enable signal ALE is output.
I/O port pin P40 (Note 4)
Clock
φ1 is output.
I/O port pin P41 (Note 4)
Hold acknowledge signal HLDA is output.
I/O port pin P42 (Note 4)
Hold request signal HOLD is input.
I/O port pin P43 (Note 4)
Chip select signal CS0 is output.
I/O port pin P91 to P93
Chip select signals CS1 to CS3 are output (Note 6).
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