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參數(shù)資料
| 型號(hào)： | M37920FCCGP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 135/158頁(yè) |
| 文件大?。?/td> | 1261K |
| 代理商： | M37920FCCGP |
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M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
78
Fig. 72 Burst transfer example (in edge sense mode)
DMAREQ0
DMA0 request bit
DMA0 enable bit
DMA1
DMA0
Channel 0 entire data transfer
Channel 1 entire data transfer
The above example applies on the following conditions :
DMA1
(CPU)
DMAREQ1
DMA1 request bit
DMA1 enable bit
DRAM refresh request
Bus user
refresh
DRAM
DMA request sources of DMA0 and DMA1: external source (edge sense)
Channel priority : fixed (channel 0 > channel 1)
Fig. 73 Burst transfer example (in level sense mode)
DMAREQ0
DMA0 request bit
DMA0 enable bit
(CPU)
DMA1
(CPU)
DMA1
(CPU)
The above example applies on the following conditions :
DMA request sources of DMA0 and DMA1: external source (level sense)
Channel priority : fixed (channel 0 > channel 1)
DMA0
DMAREQ1
DMA1 request bit
DMA1 enable bit
DRAM refresh request
Bus user
refresh
DRAM
When channel 1’s DMA transfer is entirely completed, the right to
use bus is once passed to the CPU, and the DMA transfer request
from channel 0 is later accepted at the end of the current bus cycle.
When bit 4 of the DMAi control register is set to “1”, the level sense
mode is selected. The level sense mode can be used only for the
DMA request from pin DMAREQi. When selecting another source,
be sure to select the edge sense mode.
In the level sense mode, the DMAi request bit is set to “1” to initiate
the DMA transfer only while pin DMAREQi’s input level is “L”. If pin
DMAREQi’s input level returns to “H” in the middie of transfer, the
DMA operation is interrupted at the end of the current transfer bus
cycle or next transfer bus cycle so that the right to use bus is re-
turned to the CPU. At this time, the DMA enable bit is not cleared.
When pin DMAREQi’s input level returns to “L”, the transfer opera-
tion is resumed at the address which is next to the point of interrup-
tion. In the level sense mode, the DMA request bit varies only with
the input level at pin DMAREQi. Therefore, while pin DMAREQi’s in-
put level is “L”, the DMA request bit remains to be “1” even if the
transfer is completed.
Figure 73 shows a burst transfer example in level sense mode.
When pin DMAREQi’s input level for channel 1 changes from “H” to
“L” during CPU operation, the DMA1 request bit will be set to “1” so
that the DMA controller will acquire the right to use bus and initiate
transfer. When pin DMAREQi’s input level returns to “H”, the DMA1
request bit is cleared to “0”. This causes the DMA transfer operation
to be interrupted and returns the right to use bus to the CPU.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37920FCCHP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920FGCGP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920FGCHP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920S4CGP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:16 BIT CMOS MICROCOMPUTER |
| M37P75C4P3 | 功能描述:汽車(chē)連接器 Pin Contact RoHS:否 制造商:Amphenol SINE Systems 產(chǎn)品:Contacts 系列:ATP 位置數(shù)量: 型式:Female 安裝風(fēng)格: 端接類(lèi)型: 觸點(diǎn)電鍍:Nickel |
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