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參數(shù)資料
| 型號： | M37920FCCGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 134/158頁 |
| 文件大?。?/td> | 1261K |
| 代理商： | M37920FCCGP |
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77
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
DMA request sources
One out of fifteen DMA request sources can be selected for each
channel. There are a total of fifteen DMA request sources. Thirteen
internal request sources (A-D conversion, UART0 transmit/receive,
UART1 transmit/receive, timers A0 to A4, timers B0 to B2), one soft-
ware DMA source issued by programs, and one external source by
input to pin DMAREQi. For DMA request source selection, use the
DMAi control register’s DMAi request source select bits (bits 0 to 3)
as shown in Figure 68. Table 18 lists the relationship between DMA
request source select bits (bits 0 to 3) and DMA request sources.
The request timing is the same as that for interrupts.
When the software DMA request source is selected with the DMA re-
quest source select bits, by writing “1” to any of the DMAC control
register H’s software DMA request bits (bits 0 through 3), the
correspomding DMA request bit is set to “1”. When a DMA request
bit has been set to “1”, the software DMA request bits are automati-
cally cleared to “0”. When the external source is selected with the
DMA request source select bits, the input from pin DMAREQi sets
the correspomding DMA request bit to “1”. The DMA transfer request
will not be accepted until both of the DMA request bit and DMA en-
able bit of the DMAC control registers L and H are “1”. Therefore, if
the DMA enable bit is “0”, no DMA request will be accepted even
when the DMA request bit is “1”. Note that the DMA enable bit is “0”
at reset. Therefore, after the DMA transfer parameter and other data
have been setup, be sure to set the DMA enable bit of the DMA
channel to be rendered valid to “1”. This assures that the transfer
request of that channel becomes valid, making the DMA transfer
enabled.
Transfer mode
Two DMA transfer modes are available: burst transfer mode and
cycle steal transfer mode. Mode selection is made variously for each
channele, using bit 2 of the DMAi mode register L. When this bit is
cleared to “0”, the burst transfer mode is selected. This mode is au-
tomatically selected after reset removal.
(1) Burst transfer mode
In the burst transfer mode, either the edge sense or level sense
mode can be selected only when the input from pin DMAREQi (ex-
b3
0
1
b2
0
1
0
1
b1
0
1
0
1
0
1
0
1
b0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DMA request source
Do not select.
External source (DMAREQi)
Software DMA source
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
UART0 receive
UART0 transmit
UART1 receive
UART1 transmit
A-D conversion
Table 18. Relationship between DMA request source select bits
(bits 3 to 0) and DMA request sources
ternal source) is selected as a request source.
When the DMAi control register’s bit 4 is cleared to “0”, the edge
sense mode is selected. The edge sense mode is automatically se-
lected after reset removal. In the edge sense mode, the DMA re-
quest bit is set to “1” at the falling edge of the input from pin
DMAREQi. In the burst transfer’s edge sense mode, the DMA re-
quest bit is cleared to “0” when any of the following conditions is sat-
isfied.
1. Channel i’s DMA enable bit is cleared to “0” (forced termination of
transfer).
2. Channel i’s DMA request bit is cleared to “0”.
3. All of channel i’s DMA transfers are completed (normal termination
of transfer).
4. “L” level is input to pin TC during channel i’s transfer (forced termi-
nation of transfer).
Figure 72 shows a burst transfer example in edge sense mode.
When a DMA request is received from a certain channel in the edge
sense mode’s burst transfer, no DMA request from the other chan-
nels will be accepted until the DMA transfer on the former channel is
completed. In this example, pin DMAREQi’s input (external source)
is selected as the DMA request source. When pin DMAREQi’s input
changes from the “H” to “L” level during CPU operation, the DMA
request bit will be set to “1” and the DMA controller will acquire the
right to use bus and initiate transfer. From high to low, the bus use
priority is for DRAM refresh, HOLD, DMA controller, and CPU.
Therefore, if a request is made by the DRAM refresh, which has a
higher priority than the DMA controller, the DMA controller halts any
ongoing transfer operation at the end of the current transfer bus
cycle and passes the right to use bus to the DRAM controller as
shown in Figure 72. Upon getting the right, the DRAM controller gen-
erates the refresh cycle. When refreshing is terminated, the DMA
controller resumes the execution of the interrupted DMA transfer at
the point of interruption. Once a DMA request is accepted in the
burst transfer mode, no request from the other channels is accepted
until the DMA transfer is entirely completed or the transfer operation
is brought to a forced stop. Therefore, even when the request bit of
channel 0, which has a high priority, is set to “1” in the middle of
transfer as shown in Figure 72, such a request will not be accepted.
(The priority is explained in the next section.)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37920FCCHP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920FGCGP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920FGCHP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920S4CGP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16 BIT CMOS MICROCOMPUTER |
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