參數(shù)資料
型號： M37920FCCGP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 17/158頁
文件大小： 1261K
代理商： M37920FCCGP
113
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
Fig. 112 Block diagram of debug function
Address compare register 0
Address compare register 1
Debug control register 0
Matching Compare register
Address matching
detect circuit
Debug control register 1
Internal data bus (DB0 to DB15)
CPU bus (Address)
Address matching
detection interrupt
DEBUG FUNCTION
When the CPU fetches an instruction code, an interrupt request will
be generated if a selected condition is satisfied, as a resultant of
comparison between a specified address and the start address
where the instruction code is stored (the contents of PG and PC).
The decision whether this condition is satisfied or not is called ad-
dress matching detection, and the interrupt generated by this detec-
tion is called an address matching detection interrupt. (For interrupt
vector addresses, refer to the section on interrupts.)
In the address matching detection, a non-maskable interrupt routine
is proceeded without execution of the original instruction which has
been allocated to the target address.
The debug function provides the following two modes:
the address matching detection mode, which is used to avoid the
area where program exists or modify a program.
the out-of-address-area detection mode, which is used to detect a
program runaway.
Figure 112 shows the block diagram of the debug function. Figures
113 and 114 show the bit configurations of the debug control regis-
ters 0, 1, and address compare registers 0,1, respectively.
The detect condition select bits of the debug control register 0 can
select one condition between the following 4 conditions. When the
selected address condition is satisfied, an address matching detec-
tion interrupt request will be generated:
(1) Address matching detection 0
The contents of PG and PC match with the address which has
been set in the address compare register 0.
(2) Address matching detection 1
The contents of PG and PC match with the address which has
been set in the address compare register 1.
(3) Address matching detection 2
The contents of PG and PC match with the address which has
been set in either of the address compare register 0 or address
compare register 1.
(4) Out-of-address-area detection
The contents of PG and PC are less than the address which has
been set in the address compare register 0 or larger than the ad-
dress which has been set in the address compare register 1.
By setting the detect enable bit of the debug control register 0 to “1”,
an address matching detection interrupt request will be generated if
any one of the above address conditions is satisfied. Clearing the
detect enable bit to “0” generates no interrupt request even if any of
the above address conditions is satisfied.
The address compare register access enable bit of the debug con-
trol register 1 must be set to “1” by the instruction just before the ac-
cess operation (read/write). Then, this bit must be cleared to “0”
(disabled) by the next instruction. While this bit = “0”, the address
compare registers 0, 1 cannot be accessed.
The address-matching-detection 2 decision bit of the debug control
register 1 decides, whether the address which has been set in the
address compare register 0 or 1 matches with the contents of PG,
PC, when the address matching detection 2 is selected. The con-
tents of this bit is invalid when address matching detection 0 or 1 is
selected.
In order to use the debug function to avoid the area where program
exists or modify a program, perform the necessary processing within
an address matching interrupt routine. As a result, the contents of
PG, PC, PS at acceptance of an address matching detection inter-
rupt request (i.e. the address at which an address matching detec-
tion condition is satisfied) have been pushed on to the stack. If a
return destination address after the interrupt processing is to be al-
tered, rewrite the contents of the stack, and then return by the RTI
instruction.
To use the debug function to detect a program runaway, set an ad-
dress area where no program exists into the address compare regis-
ters 0 and 1 by using the out-of-address-area detection. When the
CPU fetches instruction codes from this address area and executes
them, an address matching detection interrupt request will be gener-
ated.
The above debug function cannot be evaluated by a debugger, so
that the debug function must not be used while a debugger is run-
ning.
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