參數(shù)資料
型號(hào)： M37920FCCGP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 145/158頁
文件大?。?/td> 1261K
代理商： M37920FCCGP
87
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
(3) Array chain transfer mode
In the array chain transfer mode, one channel is used for the data
transfer for two or more memory blocks.
Three parameters necessary for transfer, that is, the transfer
source’s transfer start address, transfer destination’s transfer start
address, and the number of transfer bytes, must be sequentially writ-
ten into the transfer parameter memory. The transfer parameter
memory can be located in an arbitrary position in the memory space.
Figure 80 shows a transfer parameter memory map example in the
array chain transfer mode. All of the transfer parameters of the
memory blocks to be transferred must be written into the transfer pa-
rameter memory. The transfer parameter memory format is shown in
Figure 81. For 1-bus cycle transfer, the external I/O side’s param-
eters are not needed. For transfer from external memory to external
I/O, for instance, consecutively write the transfer source start ad-
dresses and the number of transfer bytes only, as shown in Figure
82. As the transfer destination’s transfer start addresses need not be
written, it is possible to save the transfer time and transfer parameter
memory area.
In the single and repeat transfer modes, the values written in the
SAR, DAR, and TCR first are retained in the internal latches. In the
array chain transfer and link array chain transfer modes, however,
these latches perform different functions.
The SAR latch serves as the transfer parameter register (hereinafter
referred to as TPR), which indicates the start address of the transfer
parameter memory. The TCR latch serves as the transfer block
counter (hereinafter referred to as TBC), which indicates the number
of transfer blocks. In the array chain transfer and link array chain
transfer modes, writing a value to an SAR address causes that value
to be written in the TPR, and writing a value to a TCR address
causes that value to be written in the TBC.
The array chain transfer operations are detailed below.
In the array chain transfer mode, also, first, set up the DMAi mode
register, DMAi control register, and DMAC control register. Write the
start address of the transfer parameter memory into the SAR. This
value is then written into the TPR. Be sure that an even-numbered
address is set to the start address. Nothing needs to be written into
the DAR. Into the TCR, write the desired number of memory blocks
to be transferred. This number is then written into the TBC. When the
DMA enable bit is set to “1” after completion of the above setup, DMA
transfer becomes enabled.
Fig. 80 Parameter memory map example in array chain transfer mode
4 bytes
Transfer source’s transfer start address 1
Transfer destination’s transfer start address 1
Number of transfer bytes 1
Transfer source’s transfer start address 2
Transfer destination’s transfer start address 2
Number of transfer bytes 2
Transfer source’s transfer start address 3
Transfer destination’s transfer start address 3
Number of transfer bytes 3
Transfer source’s transfer start address 4
Transfer destination’s transfer start address 4
Number of transfer bytes 4
Transfer
parameters
for
1
block
Fig. 81 Parameter memory format
Even-numbered
address
Dummy byte
Necessary
only in link
array chain
transfer.
Transfer source’s transfer start address (L)
Transfer source’s transfer start address (M)
Transfer source’s transfer start address (H)
Transfer parameter address (L)
Transfer parameter address (M)
Transfer parameter address (H)
Transfer destination’s transfer start address (L)
Transfer destination’s transfer start address (M)
Transfer destination’s transfer start address (H)
Transfer
parameters
for
1
block
Number of transfer bytes (L)
Number of transfer bytes (M)
Number of transfer bytes (H)
(H) = High order, (M) = Middle order, (L) = Low order
Fig. 82 Transfer parameter memory in 1 bus cycle transfer
4 bytes
Number of transfer bytes 1
Transfer source’s transfer start address 1
Number of transfer bytes 2
Transfer source’s transfer start address 2
Number of transfer bytes 3
Transfer source’s transfer start address 3
Number of transfer bytes 4
Transfer source’s transfer start address 4
Transfer
parameters
for
1
block
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M37920FCCHP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
M37920FGCGP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
M37920FGCHP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
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