![](http://datasheet.mmic.net.cn/120000/M37920FCCHP_datasheet_3558847/M37920FCCHP_92.png)
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
92
DRAM CONTROLLER
The DRAM controller directly accesses the DRAM located in the ex-
ternal chip select area (CS1, CS2, CS3).
Figure 88 shows the block diagram of the DRAM controller. Table 19
shows the functions of the DRAM-related signals, and Table 20
shows the relationship between the external data bus width and the
multiplexed addresses.
The start address, block size, external data bus width, and DRAM
space of the chip select area, which is to be accessed by the DRAM
controller, are specified by the CSj control register L, CSj control reg-
ister H, and the area CSj start address register in the chip select wait
controller. For more details, refer to the section on the chip select
wait controller.
Figure 89 shows the bit configuration of the CSj control register L
with use of the DRAM controller. Bit 4 is the DRAM space designa-
tion bit. When bit 4 is set to “1”, pins A8/MA0 to A16/MA8, A18/MA9,
A20/MA10, A22/MA11, and P94 to P96, become the output pins for the
DRAM control signals.
Figure 90 shows the bit configuration of the DRAM control register.
Bit 0 is the byte control select bit. When the device type of DRAM to
be connected is 1CAS/2W, be sure to clear this bit to “0”, and when
the device type of DRAM to be connected is 2CAS/1W, be sure to set
this bit to “1”. When the external data bus width = 8 bits, however, be
sure to clear this bit to “0”. Table 21 shows the relationship between
the byte control select bit and the pin functions. Each of Figures 91
and 92 shows an operating waveform example of the DRAM control
signals, address bus, and data buses with 1CAS/2W or 2CAS/1W
selected.
Bit 4 of the DRAM control register is the self-refresh operation select
bit and controls the DRAM self-refresh operation in the stop mode;
“0” disables the self-refresh operation in the stop mode, and “1” en-
ables the self-refresh operation. Bit 7 is the refresh timer count start
bit. The refresh timer starts counting when this bit is set to “1”.
Figure 94 shows an operating waveform example of the DRAM con-
trol signals at refresh. This refreshing method, as shown in Figure
94, is the “CAS before RAS refresh”. This method makes signal CAS
falls before signal RAS falls.
The refresh interval is determined by the refresh timer (address
A916). The refresh timer is an 8-bit timer performing a repetitive
count with the reload register. The clock source is internal clock f32.
The refresh time issues a refresh request to the BIU each time when
the refresh timer’s count value reaches 0016. Therefore, the relation-
ship between the value to be loaded into the refresh timer, n (n = 0116
to FF16), and DRAM refresh interval, m (s), is as follows:
n =
{m f(XIN) / 32} – 1
Once the BIU accepts a refresh request, it performs the bus arbitra-
tion for the CPU and DMAC and outputs the refresh enable signal to
the DRAM controller. Accordingly, the DRAM controller makes the re-
fresh cycle (CAS before RAS refresh).
In the stop mode, since the refresh timer stops counting and the
DRAM controller cannot perform the refresh operation (CAS before
RAS refresh).
For DRAM supporting the self-refresh operation, by setting the self-
refresh operation select bit to “1” before going into the stop mode,
the self-refresh operation in the stop mode can be enabled.
Figure 95 shows an operating waveform example of the DRAM con-
trol signals at self-refresh.