參數(shù)資料
型號(hào): M37920FCCGP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù): 94/158頁
文件大?。?/td> 1261K
代理商: M37920FCCGP
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
40
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
INTERRUPTS
Table 13 shows the interrupt sources and the corresponding inter-
rupt vector addresses. Reset is also described as a type of interrupt
in this section, too.
DBC and BRK instruction are interrupts used only for debugging.
Therefore, do not use these interrupts.
Interrupts other than reset, watchdog timer, zero divide, NMI, and
address matching detection all have interrupt control registers. Table
14 shows the addresses of the interrupt control registers, and Figure
22 shows the bit configuration of the interrupt control register.
The interrupt request bit is automatically cleared by the hardware
during reset or when processing an interrupt. Also, interrupt request
bits other than watchdog timer and NMI can be cleared by software.
Any of INT2 through INT0 interrupt requests is generated by an ex-
ternal input.
INT2 to INT0 are external interrupts; whether to cause an interrupt at
the input level (level sense) or at the edge (edge sense) can be se-
lected with the level/edge select bit. Furthermore, the polarity of the
interrupt input can be selected with the polarity select bit.
Timer and UART interrupts are described in the respective section.
The priorities of interrupts when multiple interrupt requests are
caused simultaneously are partially fixed by hardware, but, the other
can be adjusted by software as shown in Figure 23.
The hardware priority is fixed as the following:
reset > NMI > watchdog timer > other interrupts
Interrupts
DMA3
DMA2
DMA1
DMA0
Address matching detection interrupt
INT4 external interrupt
INT3 external interrupt
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT2 external interrupt
INT1 external interrupt
INT0 external interrupt
NMI external interrupt
Watchdog timer
DBC (Do not select.)
Break instruction (Do not select.)
Zero divide
Reset
Table 13 Interrupt sources and interrupt vector addresses
Vector addresses
00FFC016
00FFC116
00FFC216
00FFC316
00FFC416
00FFC516
00FFC616
00FFC716
00FFCA16
00FFCB16
00FFD016
00FFD116
00FFD216
00FFD316
00FFD416
00FFD516
00FFD616
00FFD716
00FFD816
00FFD916
00FFDA16
00FFDB16
00FFDC16
00FFDD16
00FFDE16
00FFDF16
00FFE016
00FFE116
00FFE216
00FFE316
00FFE416
00FFE516
00FFE616
00FFE716
00FFE816
00FFE916
00FFEA16
00FFEB16
00FFEC16
00FFED16
00FFEE16
00FFEF16
00FFF016
00FFF116
00FFF216
00FFF316
00FFF416
00FFF516
00FFF616
00FFF716
00FFF816
00FFF916
00FFFA16
00FFFB16
00FFFC16
00FFFD16
00FFFE16
00FFFF16
Fig. 22 Bit configuration of interrupt control register
76543210
Interrupt priority level
Interrupt request bit
0 : No interrupt requested
1 : Interrupt requested
76543210
Interrupt priority level
Interrupt request bit
0 : No interrupt requested
1 : Interrupt requested
Polarity select bit
0 : Interrupt request bit is set to “1” at “H” level when level sense is selected;
this bit is set to “1” at falling edge when edge sense is selected.
1 : Interrupt request bit is set to “1” at “L” level when level sense is selected;
this bit is set to “1” at rising edge when edge sense is selected.
Level/Edge select bit
0 : Edge sense
1 : Level sense
Bit configuration of interrupt control registers for DMA0 to DMA3, A-D converter, UART0, UART1,
timers A0 to A4, and timers B0 to B2, and INT3, INT4.
Bit configuration of interrupt control registers for INT0– INT2.
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