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參數(shù)資料
| 型號(hào)： | M37920FCCGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 144/158頁 |
| 文件大?。?/td> | 1261K |
| 代理商： | M37920FCCGP |
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M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
86
(2) Repeat transfer mode
In the repeat transfer mode, the single transfer is repeated. First, set
up the number of bits per 1 transfer unit, transfer method, transfer
mode, and transfer address direction by using the DMAi mode regis-
ter L. Next, write the transfer source block’s transfer start address in
the SAR and the transfer destination block’s transfer start address in
the DAR. Further, write the desired number of bytes to be trans-
ferred, into the TCR, and set up the DMAi control register and DMAC
control register. The DMA request is now acceptable. When the DMA
request occurs in this state, DMA transfer starts. Even when the
number of remaining bytes, which was read from the TCR, becomes
0, the DMA enable bit is not cleared to “0”. When the burst transfer
mode is selected, the DMA request bit is not cleared to “0”, also.
When the cycle steal transfer mode is selected, the DMA request bit
is cleared to “0” each time when 1-transfer-unit data has been trans-
ferred.
Fig. 79 Timing diagram example in repeat transfer mode (burst transfer mode)
φ1
ALE
RD
DMAACKi
TC
sar
dar
sar + 4
dar + 4
sar
dar
H
BLW
BHW
(CPU)
Data0
Data1
Data2
L
H
L
H
L
H
sar
sar + 5
Data0
Data1
Data2
dar
dar + 5
L
H
L
H
L
H
A0–A23
D0–D7
D8–D15
Transfer of 1 transfer unit
Data0L
Data0H
Data0L
Data0H
Data2L
Data2H
Data2L
Data2H
Data0L
Data0H
q This example applies on the following conditions:
External data bus width
: 16 bits
Transfer unit
: 16 bits
Transfer method
: 2-bus cycle transfer
Transfer source address direction
: Forward
Transfer destination address direction
: Forward
Transfer source area’s wait
: 0 wait
Transfer destination area’s wait
sar
dar
Value which has been set to TCR
Bus user
: 0 wait
: Value which has been set to SARi (even)
: Value which has been set to DARi (even)
: 6
: CPU
→ DMAC
Transfer destination
memory
Transfer source
memory
Transfer
Transfer of entire data (first)
Transfer of entire data (second)
The values written in the SAR, DAR, and TCR first are retained in the
internal latches. The contents of the latches are transferred to the
SAR, DAR and TCR at the end of the last transfer cycle. Therefore,
when the burst transfer mode is selected, the transfer operation is re-
peated starting with the values written first. When the cycle steal
transfer mode is selected, these values are used as the initial values
and transfer is performed each time the DMA request bit is set to “1”.
To forcedly terminate transfer, input “L” level to the pin TC or write the
value “0” to the DMA enable bit.
In the repeat transfer mode, TC signal output and the setting the in-
terrupt request bit of the DMA interrupt control register to “1” are not
performed.
Figure 78 shows the timing diagram example in the repeat transfer
mode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37920FCCHP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920FGCGP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920FGCHP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920S4CGP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16 BIT CMOS MICROCOMPUTER |
| M37P75C4P3 | 功能描述:汽車連接器 Pin Contact RoHS:否 制造商:Amphenol SINE Systems 產(chǎn)品:Contacts 系列:ATP 位置數(shù)量: 型式:Female 安裝風(fēng)格: 端接類型: 觸點(diǎn)電鍍:Nickel |
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