參數(shù)資料
型號(hào): M37920FCCGP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù): 62/158頁
文件大?。?/td> 1261K
代理商: M37920FCCGP
Corrections and Supplementary Explanation for M37920FxC Datasheet (REV.A) NO.2
Page
Error
Correction
(2/6)
Page 9,
Fig. 1
Fig. 2. Memory map of M37920FCCGP and
M37920FCCHP (Single-chip mode)
Fig. 1. Memory map of M37920FCCGP and
M37920FCCHP (Single-chip mode)
Memory map of M37920F8CGP and M37920F8CHP
(Single-chip mode)
(Deleted)
Fig. 3. Memory map of M37920FGCGP and
M37920FGCHP (Single-chip mode)
Fig. 2. Memory map of M37920FGCGP and
M37920FGCHP (Single-chip mode)
Page 10,
Fig. 2
Page 11,
Fig. 4;
address
0016, 0116
00000016
00000116
00000016
00000116
Reserved area (Note)
b31
b0
DB
Data buffer
b31
b0
DQ
Data buffer
Page 18,
Fig. 8
Data buffer
Temporarity stores data which has been ,
and external areas by the BIU or which is to be
writeen to internal memory, .
Temporarily stores data which has been ,
and external areas by the BIU; or temporarily
stores data which is to be written to internal
memory, .
Page 18,
Table 1
Instruction
queue buffer
Temporarity stores an instruction which .
Temporarily stores an instruction which .
(this contents is published for one page)
ALE is an address latch enable signal.
Note: The chip select wait controller, by the chip
select wait controller.
(Deleted)
The final page
of Selection of
“processor
mode”
Processor mode register 1
10
2
43
5
6
7
Recovery cycle insert select bit
HOLD input, HLDA output select
bit
0:
(P40 and P44 function as )
1:
0
ALE output select bit
RDY input select bit
Direct page register switch bit
Page 28,
Fig. 12
Processor mode register 1
10
2
43
5
6
7
Recovery cycle insert select bit
(Notes 2 and 3)
HOLD input, HLDA output
select bit (Notes 2 to 4)
0:
(P43 and P44 function as )
1:
0
ALE output select bit (Notes 2
and 3)
RDY input select bit (Notes 2
to 4)
Direct page register switch bit
(Note 1)
Internal ROM access wait bit
Internal ROM access wait bit
(Note 5)
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