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參數(shù)資料
| 型號(hào)： | M37920FCCGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 95/158頁(yè) |
| 文件大小： | 1261K |
| 代理商： | M37920FCCGP |
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41
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
Interrupts caused by the address matching detection and when di-
viding by zero are software interrupts and are not included in Figure
23.
Other interrupts previously mentioned are A-D converter, UART, etc.
interrupts. The priority of these interrupts can be changed by chang-
ing the priority level in the corresponding interrupt control register by
software.
Figure 24 shows a diagram of the interrupt priority detection circuit.
When an interrupt is caused, each interrupt device compares its own
priority with the priority from above and if its own priority is higher,
then it sends the priority below and requests the interrupt. If the pri-
orities are the same, the one above has priority.
This comparison is repeated to select the interrupt with the highest
priority among the interrupts that are being requested. Finally the
selected interrupt is compared with the processor interrupt priority
level (IPL) contained in the processor status register (PS) and the
request is accepted if it is higher than IPL and the interrupt disable
flag I is “0”. The request is not accepted if flag I is “1”. The reset, NMI,
and watchdog timer interrupts are not affected by the interrupt dis-
able flag I.
When an interrupt is accepted, the contents of the processor status
register (PS) is saved to the stack and the interrupt disable flag I is
set to “1”.
Furthermore, the interrupt request bit of the accepted interrupt is
cleared to “0” and the processor interrupt priority level (IPL) in the
processor status register (PS) is replaced by the priority level of the
accepted interrupt.
Therefore, multi-level priority interrupts are possible by resetting the
interrupt disable flag I to “0” and enable further interrupts.
For reset, watchdog timer, zero divide, NMI, and address match de-
Table 14. Addresses of interrupt control registers
Interrupt control registers
INT3 interrupt control register
INT4 interrupt control register
A-D interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2 interrupt control register
DMA0 interrupt control register
DMA1 interrupt control register
DMA2 interrupt control register
DMA3 interrupt control register
Addresses
00006E16
00006F16
00007016
00007116
00007216
00007316
00007416
00007516
00007616
00007716
00007816
00007916
00007A16
00007B16
00007C16
00007D16
00007E16
00007F16
0000B216
0000B316
0000B416
0000B516
tection interrupts, which do not have an interrupt control register, the
processor interrupt level (IPL) is set as shown in Table 15.
The interrupt request bit and the interrupt priority level of each inter-
rupt source are sampled and latched at each operation code fetch
cycle while
φ is “H”. However, no sampling pulse is generated until
the cycles whose number is selected by software has passed, even
if the next operation code fetch cycle is generated. The detection of
an interrupt which has the highest priority is performed during that
time.
Fig. 23 Interrupt priority
Fig. 24 Interrupt priority detection
Watchdog
timer
NMI
Priority is determined by hardware
A-D converter, UART, etc. interrupts
Priority can be changed by software inside .
Reset
Reset
A-D
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT2
NMI
Watchdog timer
IPL
Interrupt request
Level 0
Interrupt disable flag I
INT3
INT1
INT2
INT1
INT0
INT4
DMA1
DMA0
DMA2
DMA3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37920FCCHP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920FGCGP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920FGCHP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920S4CGP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16 BIT CMOS MICROCOMPUTER |
| M37P75C4P3 | 功能描述:汽車連接器 Pin Contact RoHS:否 制造商:Amphenol SINE Systems 產(chǎn)品:Contacts 系列:ATP 位置數(shù)量: 型式:Female 安裝風(fēng)格: 端接類型: 觸點(diǎn)電鍍:Nickel |
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