參數(shù)資料
型號: MFRC52301HN1
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Contactless reader IC
封裝: MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁數(shù): 20/98頁
文件大小: 1666K
代理商: MFRC52301HN1
MFRC523
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
20 of 98
NXP Semiconductors
MFRC523
Contactless reader IC
8.3.4.7
Register read access
To read out data from a specific register address in the MFRC523, the host controller must
use the following procedure:
Firstly, a write access to the specific register address must be performed as indicated
in the frame that follows
The first byte of a frame indicates the device address according to the I
2
C-bus rules
The second byte indicates the register address. No data bytes are added
The Read/Write bit is 0
After the write access, read access can start. The host sends the device address of the
MFRC523. In response, the MFRC523 sends the content of the read access register. In
one frame all data bytes can be read from the same register address. This enables fast
FIFO buffer access or register polling.
The Read/Write (R/W) bit is set to logic 1.
Fig 17. Register read and write access
001aak592
S
A
0
0
I
2
C-BUS
SLAVE ADDRESS
[A7:A0]
JOINER REGISTER
ADDRESS [A5:A0]
write cycle
0
(W)
A
DATA
[7:0]
[0:n]
[0:n]
[0:n]
A
P
S
A
0
0
I
2
C-BUS
SLAVE ADDRESS
[A7:A0]
JOINER REGISTER
ADDRESS [A5:A0]
read cycle
optional, if the previous access was on the same register address
0
(W)
A
P
P
S
S
start condition
P
stop condition
A
acknowledge
A
not acknowledge
W
write cycle
R
read cycle
A
I
2
C-BUS
SLAVE ADDRESS
[A7:A0]
sent by master
sent by slave
DATA
[7:0]
1
(R)
A
DATA
[7:0]
A
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