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| 型號： | MFRC52301HN1 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Contactless reader IC |
| 封裝： | MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html& |
| 文件頁數(shù)： | 44/98頁 |
| 文件大?。?/td> | 1666K |
| 代理商： | MFRC52301HN1 |
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MFRC523
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
44 of 98
NXP Semiconductors
MFRC523
Contactless reader IC
9.2.1.14
BitFramingReg register
Adjustments for bit-oriented frames.
Table 48.
Bit
Symbol
Access
Table 49.
Bit
7
9.2.1.15
CollReg register
Defines the first bit-collision detected on the RF interface.
Table 50.
Bit
Symbol
Access
Table 51.
Bit
7
BitFramingReg register (address 0Dh); reset value: 00h bit allocation
7
6
5
4
StartSend
RxAlign[2:0]
W
R/W
3
2
1
0
reserved
-
TxLastBits[2:0]
R/W
BitFramingReg register bit descriptions
Symbol
Value Description
StartSend
1
starts the transmission of data
only valid in combination with the Transceive command
used for reception of bit-oriented frames: defines the bit
position for the first bit received to be stored in the FIFO buffer
example:
LSB of the received bit is stored at bit position 0, the second
received bit is stored at bit position 1
LSB of the received bit is stored at bit position 1, the second
received bit is stored at bit position 2
LSB of the received bit is stored at bit position 7, the second
received bit is stored in the next byte that follows at bit
position 0
These bits are only to be used for bitwise anticollision at
106 kBd, for all other modes they are set to 0
reserved for future use
used for transmission of bit oriented frames: defines the
number of bits of the last byte that will be transmitted. 000b
indicates that all bits of the last byte will be transmitted
6 to 4
RxAlign[2:0]
0
1
7
3
2 to 0
reserved
TxLastBits[2:0]
-
-
CollReg register (address 0Eh); reset value: xxh bit allocation
7
6
ValuesAfterColl
reserved
CollPosNotValid
R/W
-
5
4
3
2
1
0
CollPos[4:0]
R
R
CollReg register bit descriptions
Symbol
ValuesAfterColl
Value
0
Description
all received bits will be cleared after a collision
only used during bitwise anticollision at 106 kBd,
otherwise it is set to logic 1
reserved for future use
no collision detected or the position of the collision is
out of the range of CollPos[4:0]
6
5
reserved
CollPosNotValid
-
1
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| MFRC52301HN1,151 | 功能描述:RFID應(yīng)答器 IC TRANSMISSION MOD 32-HVQFN RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| MFRC52301HN1,157 | 功能描述:RFID應(yīng)答器 IC TRANSMISSION MOD 32-HVQFN RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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| MFRC52302HN1,151 | 功能描述:RFID應(yīng)答器 CONTACTLESS READER IC RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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