參數(shù)資料
型號: MFRC52301HN1
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Contactless reader IC
封裝: MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁數(shù): 40/98頁
文件大?。?/td> 1666K
代理商: MFRC52301HN1
MFRC523
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
40 of 98
NXP Semiconductors
MFRC523
Contactless reader IC
9.2.1.7
ErrorReg register
Error bit register showing the error status of the last command executed.
Table 34.
Bit
Symbol
Access
Table 35.
Bit Symbol
7
WrErr
[1]
Command execution clears all error bits except the TempErr bit. Cannot be set by software.
9.2.1.8
Status1Reg register
Contains status bits of the CRC, interrupt and FIFO buffer.
Table 36.
Bit
Symbol
Access
ErrorReg register (address 06h); reset value: 00h bit allocation
7
6
5
WrErr
TempErr
reserved
BufferOvfl
R
R
-
4
3
2
1
0
CollErr
R
CRCErr
R
ParityErr
R
ProtocolErr
R
R
ErrorReg register bit descriptions
Value Description
1
data is written into the FIFO buffer by the host during the MFAuthent
command or if data is written into the FIFO buffer by the host during the
time between sending the last bit on the RF interface and receiving the
last bit on the RF interface
TempErr
[1]
1
internal temperature sensor detects overheating, in which case the
antenna drivers are automatically switched off
reserved
-
reserved for future use
BufferOvfl
1
the host or a MFRC523’s internal state machine (e.g. receiver) tries to
write data to the FIFO buffer even though it is already full
CollErr
1
a bit-collision is detected
cleared automatically at receiver start-up phase
only valid during the bitwise anticollision at 106 kBd
always set to logic 0 during communication protocols at 212 kBd,
424 kBd and 848 kBd
CRCErr
1
the RxModeReg register’s RxCRCEn bit is set and the CRC calculation
fails
automatically cleared to logic 0 during receiver start-up phase
ParityErr
1
parity check failed
automatically cleared during receiver start-up phase
only valid for ISO/IEC 14443 A/MIFARE communication at 106 kBd
ProtocolErr
1
set to logic 1 if the SOF is incorrect
automatically cleared during receiver start-up phase
bit is only valid for 106 kBd
during the MFAuthent command, the ProtocolErr bit is set to logic 1 if the
number of bytes received in one data stream is incorrect
6
5
4
3
2
1
0
Status1Reg register (address 07h); reset value: 21h bit allocation
7
6
5
reserved
CRCOk
CRCReady
-
R
R
4
3
2
1
0
IRq
R
TRunning
R
reserved
-
HiAlert
R
LoAlert
R
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