參數(shù)資料
型號: MFRC52301HN1
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Contactless reader IC
封裝: MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁數(shù): 55/98頁
文件大小: 1666K
代理商: MFRC52301HN1
MFRC523
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
55 of 98
NXP Semiconductors
MFRC523
Contactless reader IC
9.2.3
Page 2: Configuration
9.2.3.1
Reserved register 20h
Functionality is reserved for future use.
Table 86.
Bit
Symbol
Access
Table 87.
Bit
7 to 0
9.2.3.2
CRCResultReg registers
Shows the MSB and LSB values of the CRC calculation.
Remark:
The CRC is split into two 8-bit registers.
Table 88.
Bit
Symbol
Access
Table 89.
Bit
7 to 0
Table 90.
Bit
Symbol
Access
Table 91.
Bit
7 to 0
Reserved register (address 20h); reset value: 00h bit allocation
7
6
5
4
3
2
1
0
reserved
-
Reserved register bit descriptions
Symbol
Description
reserved
reserved for future use
CRCResultReg (higher bits) register (address 21h); reset value: FFh bit allocation
7
6
5
4
CRCResultMSB[7:0]
R
3
2
1
0
CRCResultReg register higher bit descriptions
Symbol
Description
CRCResultMSB[7:0] shows the value of the CRCResultReg register’s most
significant byte. Only valid if Status1Reg register’s CRCReady
bit is set to logic 1
CRCResultReg (lower bits) register (address 22h); reset value: FFh bit allocation
7
6
5
4
CRCResultLSB[7:0]
R
3
2
1
0
CRCResultReg register lower bit descriptions
Symbol
Description
CRCResultLSB[7:0]
shows the value of the least significant byte of the CRCResultReg
register. Only valid if Status1Reg register’s CRCReady bit is set to
logic 1
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