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| 型號： | MFRC52301HN1 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Contactless reader IC |
| 封裝： | MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html& |
| 文件頁數(shù)： | 59/98頁 |
| 文件大?。?/td> | 1666K |
| 代理商： | MFRC52301HN1 |
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MFRC523
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
59 of 98
NXP Semiconductors
MFRC523
Contactless reader IC
Table 107. TModeReg register bit descriptions
Bit
Symbol
7
TAuto
Table 108. TPrescalerReg register (address 2Bh); reset value: 00h bit allocation
Bit
7
6
5
Symbol
Access
Value Description
1
the timer starts automatically at the end of the transmission in
all communication modes at all speeds or when InvTxnRFOn
bits are set to logic 1 and the RF field is switched on
when RxMultiple bit in register RxModeReg is logic 0: in
MIFARE mode and ISO/IEC 14443 B at 106 kBd, the timer
stops after the 5
th
bit (1 start bit, 4 data bits). In all other
modes, the timer stops after the 4
th
bit
if the RxMultiple bit is set to logic 1, the timer never stops. In
this case the timer can be stopped by setting the TStopNow
bit in register ControlReg to logic 1
0
indicates that the timer is not influenced by the protocol
internal timer is runs in gated or non-gated mode
Remark:
in gated mode, the Status1Reg register’s TRunning
bit is logic 1 when the timer is enabled by the TModeReg
register bits
these bits do not influence the gating signal
00
non-gated mode
01
gated by pin MFIN
10
gated by pin AUX1
11
-
1
timer automatically restarts its count-down from the 16-bit
timer reload value instead of counting down to zero
0
timer decrements to 0 and the ComIrqReg register’s
TimerIRq bit is set to logic 1
TPrescaler_Hi[3:0] -
defines the higher 4 bits of the TPrescaler value
the following formula is used to calculate f
Timer
if
TPrescalEven bit in Demod Reg is set to logic 0:
f
Timer
= 13.56 MHz / (2 * TPreScaler + 1).
where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo]
(TPrescaler value on 12 bits). The default TPrescalEven is
logic 0
the following formula is used to calculate f
Timer
if
TPrescalEven bit in Demod Reg is set to logic 1:
f
Timer
= 13.56 MHz / (2 * TPreScaler + 2); see
Section 8.7
“Timer unit”
6 to 5
TGated[1:0]
4
TAutoRestart
3 to 0
4
3
2
1
0
TPrescaler_Lo[7:0]
R/W
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