參數(shù)資料
型號(hào): MFRC52301HN1
廠商: NXP Semiconductors N.V.
元件分類(lèi): 通信及網(wǎng)絡(luò)
英文描述: Contactless reader IC
封裝: MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁(yè)數(shù): 43/98頁(yè)
文件大?。?/td> 1666K
代理商: MFRC52301HN1
MFRC523
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
43 of 98
NXP Semiconductors
MFRC523
Contactless reader IC
Table 43.
Bit
7
9.2.1.12
WaterLevelReg register
Defines the level for FIFO under- and overflow warning.
Table 44.
Bit
Symbol
Access
Table 45.
Bit
7 to 6
5 to 0
9.2.1.13
ControlReg register
Miscellaneous control bits.
Table 46.
Bit
Symbol
Access
Table 47.
Bit
7
6
5 to 3
2 to 0
FIFOLevelReg register bit descriptions
Symbol
Value
FlushBuffer
1
Description
immediately clears the internal FIFO buffer’s read and write
pointer and ErrorReg register’s BufferOvfl bit. Reading this bit
always returns 0
indicates the number of bytes stored in the FIFO buffer. Writing to
the FIFODataReg register increments and reading decrements
the FIFOLevel value
6 to 0 FIFOLevel[6:0]
-
WaterLevelReg register (address 0Bh); reset value: 08h bit allocation
7
6
5
4
reserved
-
3
2
1
0
WaterLevel[5:0]
R/W
WaterLevelReg register bit descriptions
Symbol
Description
reserved
reserved for future use
WaterLevel[5:0]
defines a warning level to indicate a FIFO buffer overflow or underflow:
Status1Reg register’s HiAlert bit is set to logic 1 if the remaining
number of bytes in the FIFO buffer space is equal to, or less than the
defined number of WaterLevel[5:0] bits
Status1Reg register’s LoAlert bit is set to logic 1 if equal to, or less
than the WaterLevel[5:0] bits in the FIFO buffer
Remark:
to calculate values for HiAlert and LoAlert, see
Section 9.2.1.9 on page 41
.
ControlReg register (address 0Ch); reset value: 10h bit allocation
7
6
5
TStopNow
TStartNow
W
W
4
3
2
1
0
reserved
-
RxLastBits[2:0]
R
ControlReg register bit descriptions
Symbol
Value
TStopNow
1
TStartNow
1
reserved
-
RxLastBits[2:0]
-
Description
timer stops immediately
timer starts immediately. Reading this bit always returns it to 0
reserved for future use
indicates the number of valid bits in the last received byte. If this
value is zero, the whole byte is valid
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