參數(shù)資料
型號(hào): MFRC52301HN1
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Contactless reader IC
封裝: MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁(yè)數(shù): 22/98頁(yè)
文件大?。?/td> 1666K
代理商: MFRC52301HN1
MFRC523
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
22 of 98
NXP Semiconductors
MFRC523
Contactless reader IC
8.3.4.11
Switching between F/S mode and HS mode
After reset and initialization, the MFRC523 is in Fast mode (which is in effect F/S mode as
Fast mode is downward-compatible with Standard mode). The connected MFRC523
recognizes the “S 00001XXX A” sequence and switches its internal circuitry from the Fast
mode setting to the HS mode setting.
The following actions are taken:
1. Adapt the SDA and SCL input filters according to the spike suppression requirement
in HS mode.
2. Adapt the slope control of the SDA output stages.
It is possible for system configurations that do not have other I
2
C-bus devices involved in
the communication to switch to HS mode permanently. This is implemented by setting
Status2Reg register’s I
2
CForceHS bit to logic 1. In permanent HS mode, the master code
is not required to be sent. This is not defined in the specification and must only be used
when no other devices are connected on the bus. In addition, spikes on the I
2
C-bus lines
must be avoided because of the reduced spike suppression.
8.3.4.12
MFRC523 in lower speed modes
MFRC523 is fully downward-compatible and can be connected to an F/S mode I
2
C-bus
system. The device stays in F/S mode and communicates at F/S mode speeds because a
master code is not transmitted in this configuration.
Fig 19. I
2
C-bus HS mode protocol frame
msc618
8-bit master code 0000 1xxx
A
t
H
t
1
S
F/S mode
HS mode
If P then
F/S mode
If Sr (dotted lines)
then HS mode
1
6
7
8
9
6
7
8
9
1
1
2 to 5
2 to 5
2 to 5
6
7
8
9
SDA high
SCL high
SDA high
SCL high
t
H
t
FS
Sr
Sr P
n + (8-bit data + A/A)
7-bit SLA
R/W
A
= Master current source pull-up
= Resistor pull-up
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