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| 型號： | MFRC52301HN1 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Contactless reader IC |
| 封裝： | MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html& |
| 文件頁數(shù)： | 30/98頁 |
| 文件大?。?/td> | 1666K |
| 代理商： | MFRC52301HN1 |
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MFRC523
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
30 of 98
NXP Semiconductors
MFRC523
Contactless reader IC
The timer can be started manually using the ControlReg register’s TStartNow bit and
stopped using the ControlReg register’s TStopNow bit.
The timer can also be activated automatically to meet any dedicated protocol
requirements, by setting the TModeReg register’s TAuto bit to logic 1.
The delay time of a timer stage is set by the reload value + 1. The total delay time (t
d
) is
calculated using
Equation 5
:
(5)
or if the TPrescalEven bit is set, using
Equation 6
:
(6)
An example of calculating total delay time (t
d
) is shown in
Equation 7
, where the
TPrescaler value = 4095 and TReloadVal = 65535:
(7)
Example:
To give a delay time of 25
s requires 339 clock cycles to be counted and a
TPrescaler value of 169. This configures the timer to count up to 65535 time-slots for
every 25
s period.
8.8 Power reduction modes
8.8.1
Hard power-down
Hard power-down is enabled when pin NRSTPD is LOW. This turns off all internal current
sinks including the oscillator. All digital input buffers are separated from the input pins and
clamped internally (except pin NRSTPD). The output pins are frozen at either a HIGH or
LOW level.
8.8.2
Soft power-down mode
Soft power-down mode is entered immediately after the CommandReg register’s
PowerDown bit is set to logic 1. All internal current sinks are switched off, including the
oscillator buffer. However, the digital input buffers are not separated from the input pins
and keep their functionality. The digital output pins do not change their state.
During soft power-down, all register values, the FIFO buffer content and the configuration
keep their current contents.
After setting the PowerDown bit to logic 0, it takes 1024 clocks until the Soft power-down
mode is exited indicated by the PowerDown bit. Setting it to logic 0 does not immediately
clear it. It is automatically cleared by the MFRC523 when Soft power-down mode is
exited.
Remark:
When the internal oscillator is used, time (t
osc
) is required for the oscillator to
become stable. This is because the internal oscillator is supplied by V
DDA
and any clock
cycles will not be detected by the internal logic until V
DDA
is stable. It is recommended for
the serial UART, to first send the value 55h to the MFRC523. The oscillator must be stable
t
d
---------------------------------------------------------------------------------------------------------
13.56 MHz
=
t
d
---------------------------------------------------------------------------------------------------------
13.56 MHz
=
39.59 s
----------------------------------------------------------------------
13.56 MHz
=
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| MFRC52301HN1,151 | 功能描述:RFID應(yīng)答器 IC TRANSMISSION MOD 32-HVQFN RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| MFRC52301HN1,157 | 功能描述:RFID應(yīng)答器 IC TRANSMISSION MOD 32-HVQFN RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| MFRC52301HN1/TRAYB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Contactless reader IC |
| MFRC52301HN1/TRAYBM | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Contactless reader IC |
| MFRC52302HN1,151 | 功能描述:RFID應(yīng)答器 CONTACTLESS READER IC RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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