參數(shù)資料
型號: MFRC52301HN1
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Contactless reader IC
封裝: MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁數(shù): 47/98頁
文件大?。?/td> 1666K
代理商: MFRC52301HN1
MFRC523
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
47 of 98
NXP Semiconductors
MFRC523
Contactless reader IC
9.2.2.3
TxModeReg register
Defines the data rate during transmission.
Table 58.
Bit
Symbol
Access
Table 59.
Bit
7
9.2.2.4
RxModeReg register
Defines the data rate during reception.
Table 60.
Bit
Symbol
Access
Table 61.
Bit
7
TxModeReg register (address 12h); reset value: 00h bit allocation
7
6
5
TxCRCEn
TxSpeed[2:0]
R/W
D
4
3
2
1
0
InvMod
R/W
TxFraming
D
TxModeReg register bit descriptions
Symbol
TxCRCEn
Value
1
Description
enables CRC generation during data transmission
Remark:
can only be set to logic 0 at 106 kBd
defines the bit rate during data transmission
the MFRC523 handles transfer speeds up to
848 kBd
106 kBd
212 kBd
424 kBd
848 kBd
reserved
reserved
reserved
reserved
modulation of transmitted data is inverted
defines the framing used for data transmission
ISO/IEC 14443 A/MIFARE
reserved
reserved
ISO/IEC 14443 B
6 to 4
TxSpeed[2:0]
000
001
010
011
100
101
110
111
1
3
2 to 0
InvMod
TxFraming[1:0]
00
01
10
11
RxModeReg register (address 13h); reset value: 00h bit allocation
7
6
5
RxCRCEn
RxSpeed[2:0]
R/W
D
4
3
2
1
RxFraming
D
0
RxNoErr
R/W
RxMultiple
R/W
RxModeReg register bit descriptions
Symbol
Value
RxCRCEn
1
Description
enables the CRC calculation during reception
Remark:
can only be set to logic 0 at 106 kBd
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