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| 型號： | MFRC52301HN1 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Contactless reader IC |
| 封裝： | MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html& |
| 文件頁數(shù)： | 42/98頁 |
| 文件大小： | 1666K |
| 代理商： | MFRC52301HN1 |
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MFRC523
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
42 of 98
NXP Semiconductors
MFRC523
Contactless reader IC
9.2.1.10
FIFODataReg register
Input and output of 64 byte FIFO buffer.
Table 40.
Bit
Symbol
Access
Table 41.
Bit
7 to 0
9.2.1.11
FIFOLevelReg register
Indicates the number of bytes stored in the FIFO.
Table 42.
Bit
Symbol
Access
6
I
2
CForceHS
I
2
C-bus input filter settings:
the I
2
C-bus input filter is set to the High-speed mode
independent of the I
2
C-bus protocol
the I
2
C-bus input filter is set to the I
2
C-bus protocol used
reserved
indicates that the MIFARE Crypto1 unit is switched on and
all data communication with the card is encrypted; this bit is
cleared by software; can only be set to logic 1 by a
successful execution of the MFAuthent command only valid
in Read/Write mode for MIFARE standard cards
shows the state of the transmitter and receiver state
machines:
idle
wait for the BitFramingReg register’s StartSend bit
TxWait: wait until RF field is present if the TModeReg
register’s TxWaitRF bit is set to logic 1. The minimum
time for TxWait is defined by the TxWaitReg register
transmitting
RxWait: wait until RF field is present if the TModeReg
register’s TxWaitRF bit is set to logic 1. The minimum
time for RxWait is defined by the RxWaitReg register
wait for data
receiving
1
0
-
-
5 to 4
3
reserved
MFCrypto1On
2 to 0
ModemState[2:0]
-
000
001
010
011
100
101
110
Table 39.
Bit
Status2Reg register bit descriptions
…continued
Symbol
Value
Description
FIFODataReg register (address 09h); reset value: xxh bit allocation
7
6
5
FIFOData[7:0]
4
3
2
1
0
D
FIFODataReg register bit descriptions
Symbol
Description
FIFOData[7:0]
data input and output port for the internal 64-byte FIFO buffer. FIFO
buffer acts as parallel in/parallel out converter for all serial data stream
inputs and outputs
FIFOLevelReg register (address 0Ah); reset value: 00h bit allocation
7
6
5
FlushBuffer
W
4
3
2
1
0
FIFOLevel[6:0]
R
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| MFRC52301HN1,151 | 功能描述:RFID應(yīng)答器 IC TRANSMISSION MOD 32-HVQFN RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| MFRC52301HN1,157 | 功能描述:RFID應(yīng)答器 IC TRANSMISSION MOD 32-HVQFN RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| MFRC52301HN1/TRAYB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Contactless reader IC |
| MFRC52301HN1/TRAYBM | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Contactless reader IC |
| MFRC52302HN1,151 | 功能描述:RFID應(yīng)答器 CONTACTLESS READER IC RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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