參數(shù)資料
型號(hào)： MFRC52301HN1
廠商： NXP Semiconductors N.V.
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Contactless reader IC
封裝： MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁(yè)數(shù)： 94/98頁(yè)
文件大?。?/td> 1666K
代理商： MFRC52301HN1
MFRC523
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
94 of 98
continued >>
NXP Semiconductors
MFRC523
Contactless reader IC
Table 69. RxSelReg register bit descriptions . . . . . . . . . .50
Table 70. RxThresholdReg register (address 18h); reset
value: 84h bit allocation . . . . . . . . . . . . . . . . . .51
Table 71. RxThresholdReg register bit descriptions . . . .51
Table 72. DemodReg register (address 19h); reset value:
4Dh bit allocation . . . . . . . . . . . . . . . . . . . . . . .51
Table 73. DemodReg register bit descriptions . . . . . . . . .51
Table 74. Reserved register (address 1Ah); reset value: 00h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 75. Reserved register bit descriptions . . . . . . . . . .52
Table 76. Reserved register (address 1Bh); reset value: 00h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 77. Reserved register bit descriptions . . . . . . . . . .52
Table 78. MfTxReg register (address 1Ch); reset value: 62h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 79. MfTxReg register bit descriptions . . . . . . . . . .53
Table 80. MfRxReg register (address 1Dh); reset value: 00h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 81. MfRxReg register bit descriptions . . . . . . . . . .53
Table 82. TypeBReg register (address 1Eh); reset value:
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .53
Table 83. TypeBReg register bit descriptions . . . . . . . . .53
Table 84. SerialSpeedReg register (address 1Fh); reset
value: EBh bit allocation . . . . . . . . . . . . . . . . .54
Table 85. SerialSpeedReg register bit descriptions . . . . .54
Table 86. Reserved register (address 20h); reset value: 00h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 87. Reserved register bit descriptions . . . . . . . . . .55
Table 88. CRCResultReg (higher bits) register (address
21h); reset value: FFh bit allocation . . . . . . . .55
Table 89. CRCResultReg register higher bit descriptions 55
Table 90. CRCResultReg (lower bits) register (address
22h); reset value: FFh bit allocation . . . . . . . .55
Table 91. CRCResultReg register lower bit descriptions .55
Table 92. Reserved register (address 23h); reset value: 88h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 93. Reserved register bit descriptions . . . . . . . . . .56
Table 94. ModWidthReg register (address 24h); reset value:
26h bit allocation . . . . . . . . . . . . . . . . . . . . . . .56
Table 95. ModWidthReg register bit descriptions . . . . . .56
Table 96. Reserved register (address 25h); reset value: 87h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 97. Reserved register bit descriptions . . . . . . . . . .56
Table 98. RFCfgReg register (address 26h); reset value:
48h bit allocation . . . . . . . . . . . . . . . . . . . . . . .57
Table 99. RFCfgReg register bit descriptions . . . . . . . . .57
Table 100. GsNReg register (address 27h); reset value: 88h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 101. GsNReg register bit descriptions . . . . . . . . . .57
Table 102. CWGsPReg register (address 28h); reset value:
20h bit allocation . . . . . . . . . . . . . . . . . . . . . . .58
Table 103. CWGsPReg register bit descriptions . . . . . . . 58
Table 104. ModGsPReg register (address 29h); reset value:
20h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 58
Table 105. ModGsPReg register bit descriptions . . . . . . . 58
Table 106. TModeReg register (address 2Ah); reset value:
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 58
Table 107. TModeReg register bit descriptions . . . . . . . . 59
Table 108. TPrescalerReg register (address 2Bh); reset
value: 00h bit allocation . . . . . . . . . . . . . . . . . 59
Table 109. TPrescalerReg register bit descriptions . . . . . 60
Table 110. TReloadReg (higher bits) register (address 2Ch);
reset value: 00h bit allocation . . . . . . . . . . . . . 60
Table 111. TReloadReg register higher bit descriptions . . 60
Table 112. TReloadReg (lower bits) register (address 2Dh);
reset value: 00h bit allocation . . . . . . . . . . . . . 60
Table 113. TReloadReg register lower bit descriptions . . 60
Table 114. TCounterValReg (higher bits) register (address
2Eh); reset value: xxh bit allocation . . . . . . . . 60
Table 115. TCounterValReg register higher bit
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 116. TCounterValReg (lower bits) register (address
2Fh); reset value: xxh bit allocation . . . . . . . . 61
Table 117. TCounterValReg register lower bit
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 118. Reserved register (address 30h); reset value: 00h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 119. Reserved register bit descriptions . . . . . . . . . 61
Table 120. TestSel1Reg register (address 31h); reset value:
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 61
Table 121. TestSel1Reg register bit descriptions . . . . . . . 61
Table 122. TestSel2Reg register (address 32h); reset value:
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 62
Table 123. TestSel2Reg register bit descriptions . . . . . . . 62
Table 124. TestPinEnReg register (address 33h); reset
value: 80h bit allocation . . . . . . . . . . . . . . . . . 62
Table 125. TestPinEnReg register bit descriptions . . . . . 62
Table 126. TestPinValueReg register (address 34h); reset
value: 00h bit allocation . . . . . . . . . . . . . . . . . 63
Table 127. TestPinValueReg register bit descriptions . . . 63
Table 128. TestBusReg register (address 35h); reset value:
xxh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 63
Table 129. TestBusReg register bit descriptions . . . . . . . 63
Table 130. AutoTestReg register (address 36h); reset value:
40h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 63
Table 131. AutoTestReg register bit descriptions . . . . . . . 64
Table 132. VersionReg register (address 37h); reset value:
xxh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 64
Table 133. VersionReg register bit descriptions . . . . . . . . 64
Table 134. AnalogTestReg register (address 38h); reset
value: 00h bit allocation . . . . . . . . . . . . . . . . . 64
Table 135. AnalogTestReg register bit descriptions . . . . . 65
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