參數(shù)資料
型號(hào): MFRC52301HN1
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Contactless reader IC
封裝: MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;MFRC52301HN1<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html&
文件頁(yè)數(shù): 33/98頁(yè)
文件大?。?/td> 1666K
代理商: MFRC52301HN1
MFRC523
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
33 of 98
NXP Semiconductors
MFRC523
Contactless reader IC
9.1.1
MFRC523 register overview
Table 21.
Subaddress
(Hex)
Page 0: Command and status
00h
Reserved
01h
CommandReg
02h
ComlEnReg
03h
DivlEnReg
04h
ComIrqReg
05h
DivIrqReg
06h
ErrorReg
07h
Status1Reg
08h
Status2Reg
09h
FIFODataReg
0Ah
FIFOLevelReg
0Bh
WaterLevelReg
0Ch
ControlReg
0Dh
BitFramingReg
0Eh
CollReg
MFRC523 register overview
Register name
Function
Refer to
reserved for future use
starts and stops command execution
enable and disable interrupt request control bits
enable and disable interrupt request control bits
interrupt request bits
interrupt request bits
error bits showing the error status of the last command executed
communication status bits
receiver and transmitter status bits
input and output of 64 byte FIFO buffer
number of bytes stored in the FIFO buffer
level for FIFO underflow and overflow warning
miscellaneous control registers
adjustments for bit-oriented frames
bit position of the first bit-collision detected on the RF interface
Table 22 on page 36
Table 24 on page 36
Table 26 on page 37
Table 28 on page 37
Table 30 on page 38
Table 32 on page 39
Table 36 on page 40
Table 36 on page 40
Table 38 on page 41
Table 40 on page 42
Table 42 on page 42
Table 44 on page 43
Table 46 on page 43
Table 48 on page 44
Table 50 on page 44
0Fh
Page 1: Command
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Reserved
reserved for future use
Table 52 on page 45
Reserved
ModeReg
TxModeReg
RxModeReg
TxControlReg
TxASKReg
TxSelReg
RxSelReg
RxThresholdReg
DemodReg
Reserved
Reserved
MfTxReg
MfRxReg
TypeBReg
SerialSpeedReg
reserved for future use
defines general modes for transmitting and receiving
defines transmission data rate and framing
defines reception data rate and framing
controls the antenna driver pins TX1 and TX2
controls the setting of the transmission modulation
selects the internal sources for the antenna driver
selects internal receiver settings
selects thresholds for the bit decoder
defines demodulator settings
reserved for future use
reserved for future use
controls MIFARE communication transmit parameters
controls MIFARE communication receive parameters
controls the ISO/IEC 14443 B functionality
selects the speed of the serial UART interface
Table 54 on page 45
Table 56 on page 46
Table 58 on page 47
Table 60 on page 47
Table 62 on page 48
Table 64 on page 49
Table 66 on page 49
Table 68 on page 50
Table 70 on page 51
Table 72 on page 51
Table 74 on page 52
Table 76 on page 52
Table 78 on page 52
Table 80 on page 53
Table 82 on page 53
Table 84 on page 54
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