參數(shù)資料
型號(hào)： MK68564
廠商： 意法半導(dǎo)體
英文描述： Serial Input Output(串行I/O(雙通道,多功能外圍電路))
中文描述： 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路））
文件頁(yè)數(shù)： 10/46頁(yè)
文件大?。?/td> 464K
代理商： MK68564
DATA PATH
The transmit and receive data paths for each chan-
nel are shown in figure 6. The receiver has three
8-bit bufferregisters ina FIFOarrangement (to pro-
vide a 3-byte delay) in addition to the 8-bit receive
shift register. This arrangement creates additional
timefor theCPUtoservice aninterrupt at the begin-
ning of a block of high-speed data. The receiver er-
ror FIFO storesparity and framing errors and other
types of status information for each of the three
bytes in the receivedata FIFO.The receive error FI-
FO is loaded at the same time as the receive data
FIFO. The contents of the receive error are read
through the upper four bits in Status Register 1.
Incoming data is routed through one of several
paths,depending onthemodeandcharacterlength.
In the Asynchronous modes, serial data is entered
into the 3-bit buffer, ifithasa character length ofse-
ven or eight bits, or the data is entered into the 8-bit
receive shift register, if it has a length of five or six
bits.
In the Synchronous mode, the data pathis determi-
ned by thephase ofthe receive process currently in
operation. A Synchronous Receive operation be-
gins with the receiver in the Hunt phase, during
which time the receiver searches the incoming data
stream for a bit pattern that matches the prepro-
grammed sync characters (or flags in the SDLC
mode). If the device is programmed for Monosync
Hunt, a match is madewith a single sync character
stored in Sync Word Register 2. In Bisync Hunt, a
match is made with the dual sync characters stored
in Sync Word Registers 1 and 2. In eithercase, the
incoming data passes through the receive sync re-
gister and is compared against the programmed
synccharacters in SyncWord Registers 1 and 2.
In the Monosync mode, a matchbetween the sync
character programmed into Sync Word Register 2
and thecharacter assembled in thereceive syncre-
gisterestablishes synchronization.
In the Bysync mode, incoming data is shifted to the
receive shift register, while the next eight bits of the
message are assembled in the receive sync regis-
ter.The match between theassembled character in
the syncregister and the programmed character in
Sync Word Register 2, and between the character
in the shift register and the programmed character
in Sync Word Register 1 establishes synchroniza-
tion.Once synchronization is established, incoming
data bypasses the receive syncregister anddirectly
entersthe 3-bit buffer.
In the SDLC mode, all incoming data passes
throughthereceivesyncregister,which continuous-
ly monitors the receive data stream and performs
zero deletion when indicated. Upon receiving five
contiguous ones, the sixth bit is inspected. If the
sixth bit is a 0, it is deleted fromthe data stream. If
the sixth bit is a 1, theseventh bit isinspected. If the
seventh bit is a 0, a Flag sequence has been recei-
ved ;if the seventh bitisa 1,an Abortsequence has
been received.
The reformatted data from thereceive sync register
enters the 3-bit buffer and is transferred to the re-
ceiveshiftregister. Note that theSDLCreceive ope-
rationalso begins in the Hunt Phase, during which
timetheSIO triestomatch theassembled character
in the receive sync register with the flag pattern in
SyncWord Register 2. Once the first flag character
is recognized, all subsequent data isrouted through
the path described above, regardless of character
length.
Although the same CRC checker is used for both
SDLC and synchronous data, the path taken for
each modeis different. In Bisync protocol, the byte-
oriented operation requires that the CPU decide
whether or not to include the data character in the
CRC calculation. To allow the CPU ample time to
make this decision, the SIO provides an 8-bit delay
before the data enters the CRC checker. In the
SDLCmode,nodelayisprovided, since CRCiscal-
culated on alldata between theopening and closing
flags.
The transmitter has an 8-bit transmit data register,
which is loaded from the internal bus, and a 20-bit
transmit shift register, which can be loaded from
Sync Word Register 1, Sync Word Register 2, and
the transmit data register. Sync Word Registers 1
and 2 contain sync characters in the Monosync, Bi-
sync,orExternal Sync modes, oraddress field(one
character long) and flag, respectively, in the SDLC
mode. During Synchronous modes, information
contained in Sync Word Registers 1 and2 is loaded
intothe transmit shift register at the beginning of the
message and, as a time filler, in the middle of the
message if a Transmit Underrun condition occurs.
InSDLCmode,theflagsareloaded intothetransmit
shift register at the beginning and end of the mes-
sage.
Asynchronous data in the transmit shift register is
formattedwith startandstopbits,anditisshiftedout
to thetransmit multiplexer attheselected clockrate.
Synchronous (Monosync, Bisync, or External Sync)
data is shifted outto the transmit multiplexer and al-
so the CRC generator at the x1 clock rate.
SDLC/HDLC data is shifted out through the zero in-
sertion logic, which is disabled while flags are being
sent.Forallotherfields (address, control,and frame
check),a0isinsertedfollowingfivecontiguousones
MK68564
10/46
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