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參數(shù)資料
| 型號： | MK68564 |
| 廠商： | 意法半導體 |
| 英文描述： | Serial Input Output(串行I/O(雙通道,多功能外圍電路)) |
| 中文描述： | 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路）） |
| 文件頁數(shù)： | 29/46頁 |
| 文件大?。?/td> | 464K |
| 代理商： | MK68564 |
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D4, D3 : Receive Interrupt Modes 1 and 0
Together, these two bitsspecify thevariouscharac-
ter-avalaible conditions that will cause interrupt re-
quests. When receiver interrupts are enabled, a
Special Receive Condition can cause an interrupt
request andmodify theinterrupt vector. Special Re-
ceiveconditions are:RxOverrun Error, Framing Er-
ror(inasyncmode), End OfFrame (inSDLC mode),
and Parity Error (when selected). The Rx Overrun
Error and the Parity Error conditions are latched in
Status Register1when theyoccur ;they arecleared
by an Error Reset command (Command 4) or by a
hardware or channel rest.
ReceiveInterruptsDisabled
. Thismode prevents
the receiver from generating an interrupt request
and clearsany pending receiver interrupts. Ifa char-
acter is avalaible in the receiver data FIFO, or if a
Special Receive Condition exists before or during
the time receiver interrupts are disabled, and recei-
ver interrupts are then enabled without clearing
these conditions, an interrupt request will immedi-
atelybe generated.
Receive Interrupt On First Character Only
. The
receiver requests an interrupt in this mode on the
first available character (or stored FIFO character),
or on a Special Receive Condition. If a Special Re-
ceive Condition occurs, the data with the special
conditionis heldinthereceive dataFIFOuntilan Er-
ror Reset command (Command 6) is issued.
The receive Interrupt OnFirst Character Onlymode
can be re-enabled by the Enable Interrupt On Next
Rx Character command (Command 4). If this inter-
rupt mode was terminated by a Special Receive
Condition, the Error Reset command must be is-
sued,before Command4,for proper operation to re-
sume.
Interrupt On All Receive Characters
. This mode
ammows an interrupt for every character received
(orcharacter inthe receive data FIFO)and provides
a unique vector (if Status Affects ector is enabled)
when a Special Receive Condition exists.When the
interrupt request is due to a special condition, the
data containing that condition, the data containing
data FIFO.
D2 : Status Affects Vector
Whenthis bit iszero, the value programmed intothe
Vector Register isreturned during aread cycleoran
interrupt acknowledge cycle. If the VectorRegister
has notbeen programmed following a hardware re-
set,then ”0FH”is returned.
When this bit is a one, the vector returned during a
read cycle or an interrupt acknowledge cycleis va-
riable. The variablefieldreturneddepends on the hi-
ghest-priority pending interrupt at the startofthe cy-
cle.
The Status Affects Vector control bits from both
channels arelogical ”or” edtogether;therefore, ifei-
ther is programmed to a one, its operation affects
both channels. This is the only control bit that func-
tions in this manner on the MK68564.
D1 : Transmit Interrupt Enable
When this bit is set to a one, the transmitter will re-
quest an interrupt whenever the transmit buffer be-
comes empty. When this bit is zero, no transmitter
interrupts will be requested.
Rx INT
MODE 1
0
0
Rx INT
MODE 0
0
1
1
1
0
1
Receive Interrupts Disabled
Receive Interrupt On First
Character Only
Interrupt On All Receive
Characters-parity
Error is a Special Receive
Condition
Interrupt On All Receive
Characters-parity
Error is not a Special Receive
Condition
V2
0
0
0
0
1
1
1
1
V1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
Interrupt Condition
Ch B Transmit Buffer Empty
Ch B External/statusChange
Ch B Receive Character Available
Ch B Special Receive Condition*
Ch A Transmit Buffer Empty
Ch A External/statusChange
Ch A Receive Character Available
Ch A Special Receive Condition*
*
Special Receive Conditions : Parity Error, Rx Overrun Er-
D0 : External/Status Interrupt Enable
When this bit is set to a one, an interrupt will bere-
questedbytheexternal/status logiconanyofthefol-
lowingoccurrences :a transition(high-to-low orlow-
to-high) on the DCD, CTS, or SYNC input pins, a
break/abort condition that has been detected and
MK68564
29/46
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