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參數(shù)資料
| 型號： | MK68564 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Serial Input Output(串行I/O(雙通道,多功能外圍電路)) |
| 中文描述： | 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路）） |
| 文件頁數(shù)： | 17/46頁 |
| 文件大?。?/td> | 464K |
| 代理商： | MK68564 |
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Control Register, Interrupt Control Register, Recei-
ver Control Register, Transmitter Control Register,
Sync Word 1, and Sync Word 2. The Mode Control
Register must be programmed before other regis-
ters to assure proper operation of theSIO. The fol-
lowing
registers are used to transfer data or
communicate status between the SIO and the CPU
or other bus master : Command Register, Status
Register 0, Status Register 1, Data Register, and
the Vector Register.
The SIO provides four I/O lines in Synchronous
modes that maybe used for modem control, for ex-
ternalinterrupts, oras generalpurpose I/O.The Re-
quest To Send (RTS) and Data Terminal Ready
(DTR) pins are outputs thatfollowthe inverted state
of their respective bits in the Transmit Control Re-
gister.The Data Carrier Detect (DCD) and Clear To
Send(CTS) pins areinputsthatcanbeusedasauto
enables to the receiver and transmitter, respective-
ly. If External/Status Interrupts are enabled, the
DCD and CTS pins will be monitored for a change
of status. If these inputs change for a period of time
greaterthan the minimum specified pulsewidth, an
interrupt will be generated.
In the following discussion, all interrupt modes are
assumed enabled.
SYNCHRONOUSTRANSMIT
Initialization
. Byte-oriented transmitter programs
areusuallyinitialized with thefollowing parameters :
odd-even or no parity, x1 clock mode, 8- or 16-bit
sync character(s), CRC polynomial, Transmit En-
ables, interrupt modes, and transmit character
length. If Parity is enabled, the transmitter will only
add a parity bit to a character that is loaded into the
transmit buffer ;it willnot add a parity bitto theauto-
matically inserted sync character(s) or the CRC
characters.
One of two polynomials may be used with Synchro-
nousmodes,CRC-16(X
16
+ X
15
+ X
2
+1)orSDLC-
CRC (X
16
+ X
12
+ X
5
+ 1). For either polynomial
(SDLC mode not selected), the CRC generator and
checkerare reset to all zeros. Both the receiver and
transmitter use the same polynomial.
After reset (hardware or software), or when the
transmitter is not enabled, the Transmit Data (TxD)
output pin is held High (marking). Under program
control, theSend Breakbit intheTransmitterControl
Register canbe setto a one, forcing theTxDoutput
pin to a Low level (spacing), even if the transmitter
is notenabled. Thespacingcondition willpersistun-
til the Send Break bit is reset to a zero. A program-
med break iseffectiveassoonasitiswrittenintothe
Transmit Control Register ; any characters in the
transmit buffer and transmit shift register are lost.
If thetransmitbuffer isemptywhentheTransmitEn-
able bit is set to a one, the transmitter will start sen-
ding 8-or16-bit sync characters. Continuous syncs
will be transmitted on the TxD output pin, as long as
no data is loaded into thetransmit buffer. Note, if a
Figure 10 :
Synchronous Formats.
V000383
MK68564
17/46
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