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參數(shù)資料
| 型號： | MK68564 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Serial Input Output(串行I/O(雙通道,多功能外圍電路)) |
| 中文描述： | 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路）） |
| 文件頁數(shù)： | 14/46頁 |
| 文件大?。?/td> | 464K |
| 代理商： | MK68564 |
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Figure 9 :
Asynchronous Message Format.
V000382
The SIOprovides five I/O linesthat maybe used for
modemcontrol, for externalinterrupts, orasgeneral
purpose I/O.The Request To Send (RTS) and Data
Terminal Ready (DTR) pins are outputs that follow
the inverted state of their respective bits in the
Transmitter Control Register. TheRTS pin can also
be usedtosignal theend ofamessage inAsynchro-
nous modes, as explained below in the transmitter
section. The Data Carrier Detect (DCD), Clear To
Send (CTS), and SYNC pins are inputs to the SIO
in Asynchronous modes. DCD and CTS can be u-
sed as auto enables to the receiver and transmitter,
respectively, or if External/Status Interrupts are en-
abled all three input pins will be monitored for a
change of status.If these inputs change fora period
of time greater than the minimum specified pulse
width, an interrupt will be generated.
In the following discussion, all interrupt modes are
assumed enabled.
ASYNCHRONOUS TRANSMIT
Start of Transmission
. TheSIO will start transmit-
ting data when the Transmit Enable bit is set to a
one,and acharacter has been loaded intothetrans-
mit buffer. If the TxAuto Enables bit is set, the SIO
willwait for a Low on the Clear ToSend input(CTS)
beforestarting data transmission. The Tx Auto En-
ables feature allows the programmer to send the
first data character of the message to the SIO wi-
thout waiting for CTS to go Low. In all cases, the
TransmitEnablebitmustbesetbefore transmission
can begin. The transitions on the CTSpin will gene-
rate External/Status interrupt requests and also
latch up the external/status logic. The external/sta-
tus logic should be rearmed by issuing a Reset Ex-
ternal/Status Interrupts command.
Transmit Characteristics
. The SIO automatically
inserts astartbit, theprogrammed parity bit(odd, e-
ven, or no parity), and the programmed number of
stopbits tothe datacharacter to be transmitted. The
transmitter can transmit from one to eight data bits
per character. All characters are transmitted least-
significant bit first. When the character length pro-
grammed is six orseven bits, the unused bitsof the
transmit buffer are automatically ignored. When a
character length of five bits or less is programmed,
the data loaded into the transmit buffer must be for-
matted as described in the Transmitter Control Re-
gisterpart of theRegister Descriptionsection. Serial
data isshifted out of theTxD pin on the falling edge
of the Transmit Clock (TxC) at a rate equal to 1,
1/16th, 1/32nd, or 1/64th of TxC.
Data Transfer
. TheSIOwill signal theCPUorother
bus master witha transmit interrupt request andset
the Tx Buffer Empty bit in Status Register 0, every
time the contents of the transmit buffer are loaded
intothe transmit shift register. The interrupt request
will be cleared when a new character is loaded into
the transmit buffer, or a Reset Tx Interrupt Pending
command(Command 5) isissued. IfCommand 5 is
issued, the transmit buffer willhave to be loaded be-
fore any additional transmit interrupt requests are
generated. The Tx Buffer Empty bit is reset when a
new character is loaded into the transmit buffer.
The All Sent bit inStatus Register 1 is used to indi-
cate when all data in the shift register has been
transmitted,and thetransmitbufferisempty.Thisbit
is Low, while the transmitter is sending characters,
anditwillgoHighonebittimeafterthetransmit clock
that clocks out the last stop bit of the character on
the TxD pin. No interrupts are generated by the All
Sent bit transitions. The Request To Send (RTS) bit
MK68564
14/46
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