- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377968 > MK68564 (意法半導(dǎo)體) Serial Input Output(串行I/O(雙通道,多功能外圍電路)) PDF資料下載
參數(shù)資料
| 型號： | MK68564 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Serial Input Output(串行I/O(雙通道,多功能外圍電路)) |
| 中文描述： | 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路）） |
| 文件頁數(shù)： | 35/46頁 |
| 文件大?。?/td> | 464K |
| 代理商： | MK68564 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁當(dāng)前第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
register stack called thereceive dataFIFO. TheDa-
ta Register isnotaffectedby a channel orhardware
reset.
TIME CONSTANT REGISTER (TCREG)
Thisregister contains the time constant used by the
down counter in the baud rate generator. The time
constant maybe changed at any time, but the new
valuedoesnottake effectuntil thenexttimethetime
constant is loaded into the down counter. It is re-
commended that the BRG be disabled before wri-
ting to this register, as no attempt was made to
synchronize the loading of a new timeconstant with
the clock used to drive theBRG. Thisregister is re-
set to ”00H” by a channel or hardware reset.
BAUD RATE GENERATOR CONTROL RE-
GISTER (BRGCTL)
This register contains the control bits used to pro-
gram the baud rate generator and to select the BRG
output mode. This register is reset to ”00H” by a
channel or hardware reset.
D7, D6, D5, D4 : Not Used (read as zeros)
D3 : Receiver Clock, Internal/External
This bit determines the direction of the RxC pin.
Whenthisbitissettoaone,theRxCpinistheoutput
of the baud rate generator. If this bit is a zero, the
RxC pin is an input, and an external source must
supply the receiver clock. The receiver clock is al-
ways the signal on the RxC pin, except in Loop
Mode,whenthetransmitterclockisconnected inter-
nallyto the receiver clock.
D2 : Transmitter Clock, Internal/External
This bit determines the direction of the TxC pin.
Whenthisbitissetto aone,theTxCpinisthe output
of the baud rate generator. If this bit is a zero, the
TxC pin is an input, and an external source must
supplythetransmitterclock. Thetransmit clockisal-
ways the signalon the TxCpin.
D1 : Divide By 64/4
Thisbit specifies the minimum BRG input clock cy-
cles to output clock cycle. This minimum occurs
when the Time Constant Register is loaded with a
”01H” value. When this bit is set to a one, 64 input
clocksarerequired foreveryoutput clock.Whenthis
bit is a zero, four input clocks are required for every
output clock.
D0 : Baud Rate Generator Enable
Thisbitcontrols theoperation ofthebaud rategene-
rator.When thisbit is setto a one, theBRG will start
counting down from the value leftinthedown coun-
ter when this bit was last reset to zero. If the Time
ConstantRegister isloadedwhilethisbitisreset,the
new time constant value is loaded immediately into
the down counter. The baud rate generator is disa-
bled from counting when this bit is reset.
INTERRUPT VECTOR REGISTER
(VECTRG)
Thisregister is used to holda vector that is passed
to the CPU during an interrupt acknowledge cycle.
This register can also be accessed through a
read/writecycle.IftheStatusAffectsVectorbitinthe
Interrupt Control Register isdisabled, thevalue pro-
grammed intothe Vector Register will be passed to
the CPU during an interrupt acknowledge cycle or
a read cycle. If theStatus AffectsVector bit ineither
channel isenabled, the lower three bits of this regis-
ter are modified, according to the table listed in the
Interrupt Control Register description. With Status
Affects Vector on, and no interrupt pending in the
SIO, the lower three bits will be read as 011. Only
o
n
e Vector Register existsinthe SIO,but itcanbe ac-
D7
TC7
D6
TC6
D5
TC5
D4
TC4
D3
TC3
D2
TC2
D1
TC1
D0
TC0
D7 D6 D5 D4
D3
RxC
INT/EXT
D2
TxC
D1
D0
BRG
ENABLE
INT/EXT
DIVIDE
BY 64/4
D7
V7
D6
V6
D5
V5
D4
V4
D3
V3
D2
V2
*
D1
V1
*
D0
V0
*
*
Variable if Status Affects Vectors is Enabled.
MK68564
35/46
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK68901 | Multifunction Peripheral(多功能外圍電路) |
| MK70110 | Bluetooth? Module |
| MK70120 | Bluetooth? Module |
| ML2003IQ | Logarithmic Gain/Attenuator |
| ML2003CP | Logarithmic Gain/Attenuator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK68564N-04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68564N-05 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68564Q-04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68564Q-05 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68590P | 制造商:STMicroelectronics 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。