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參數(shù)資料
| 型號： | MK68564 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Serial Input Output(串行I/O(雙通道,多功能外圍電路)) |
| 中文描述： | 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路）） |
| 文件頁數(shù)： | 18/46頁 |
| 文件大?。?/td> | 464K |
| 代理商： | MK68564 |
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character is loaded into the transmit buffer before
enabling the transmitter, that character willbe sent
in place of the synccharacter(s).
Start of Transmission
. Transmission will begin
with the loading of the first data character into the
transmit buffer, ifthe transmitter is already enabled.
For CRC to be calculated correctly on each mes-
sage,the CRC generator must be reset to all zeros
before the first data character is loaded into the
transmit buffer. This is accomplished by issuing a
Reset Tx CRC Generator command in the
Command Register.
Synchronous Transmit Characteristics
. In all
Synchronous modes, characters are sent with the
least-significant bitsfirst.Alldataisshifted out ofthe
Transmit Data pin (TxD) on the falling edge of the
Transmit Clock (TxC). The transmitter can transmit
from one to eight data bits per character. This re-
quires right-hand justification of data written to the
transmit buffer, if the selected word length is less
thaneight bitspercharacter. When theprogrammed
character length is six or sevenbits,the unused bits
in thetransmit buffer are ignored. If a word length of
five bits per character or less is selected, the data
loadedinto thetransmitbuffer mustbeformatted as
described intheTransmit Control register partofthe
Register Description section.
The number of bits per character to be transmitted
can be changed on the fly. Any data written to the
transmit buffer, after the bits per character field is
changed, are affected by the change. The same is
true of any characters in the buffer at the time the
bits per character field is changed. The change in
the number of bits per character does not affect the
character in the process of being shiftedout.
A transmitted message can be terminated by CRC
and sync characters, by sync characters only, or by
pad characters (replacing the sync character(s) in
theSync Word Registers with pad characters). How
a message is terminated is controlled by the TxUn-
derrun/EOM latch inStatus Register 0.
Figure 11a :
External SyncTiming.
Figure 11b :
Simple External Sync Delay.
V000384
V000385
MK68564
18/46
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK68564N-04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68564N-05 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68564Q-04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68564Q-05 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68590P | 制造商:STMicroelectronics 功能描述: |
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