參數(shù)資料
型號: MK68564
廠商: 意法半導(dǎo)體
英文描述: Serial Input Output(串行I/O(雙通道,多功能外圍電路))
中文描述: 串行輸入輸出(串行的I / O(雙通道,多功能外圍電路))
文件頁數(shù): 37/46頁
文件大?。?/td> 464K
代理商: MK68564
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0 VDC
±
5%, GND = 0 VDC, T
A
= 0 to 70
°
C)
4.0 MHz
Min.
250
105
105
5.0 MHz
Min.
200
80
80
Number
Parameter
Max.
1000
Max.
1000
Unit
Notes
1
2
3
4
5
6
7
8
9
10
11
CLK Period
CLK Width High
CLK Width Low
CLK Fall Time
CLK Rise Time
CS Low to CLK High (setup time)
A1-A5 Valid to CS Low (setup time)
DATA Valid to CS Low (write cycle)
CS Width High
DTACK Low to A1-A5 Invalid (hold time)
DTACK Low to DATA Invalid
(write cycle hold time)
CS High to DTACK High (delay)
CLK High to DTACK Low
R/W Valid to CS Low (setup time)
DTACK Low to R/W Invalid (hold time)
CLK Low to DATA Out
CS High to DATA Out Invalid (hold time)
CS High to DTACK High Impedance
DTACK Low to CS High
DATA Valid to DTACK Low
IACK Width High
IACK Low to CLK High (setup time)
CLK Low to INTR Disabled
CLK Low to DATA Out
DTACK Low to IACK, IEI, High
IACK High to DTACK High
IACK High to DTACK High Impedence
IACK High to DATA Out Invalid (hold time)
DATA Valid to DTACK Low
CLK Low to IEO Low
IEI Low to IEO Low
IEI High to IEO High
IACK High to IEO High
IACK High to INTR Low
IEI Low to CLK Low (setup time)
IEI Low to INTR Disabled
IEI Low to DATA Out Valid
DATA Out Valid to DTACK Low
IACK High to DATA Out High Impedence
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
30
30
30
0
0
0
50
0
0
0
0
0
50
0
0
1
1
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
55
320
50
295
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
0
450
450
0
0
11
105
100
0
70
50
0
0
70
50
0
1
1
2
2
410
330
410
330
0
55
0
50
105
100
0
0
195
195
2
3
3
4
4
5
220
140
190
190
200
220
140
190
190
200
10
10
425
225
425
225
6
6
6
55
55
120
90
MK68564
37/46
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