- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377968 > MK68564 (意法半導(dǎo)體) Serial Input Output(串行I/O(雙通道,多功能外圍電路)) PDF資料下載
參數(shù)資料
| 型號： | MK68564 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Serial Input Output(串行I/O(雙通道,多功能外圍電路)) |
| 中文描述： | 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路）） |
| 文件頁數(shù)： | 6/46頁 |
| 文件大?。?/td> | 464K |
| 代理商： | MK68564 |
第1頁第2頁第3頁第4頁第5頁當(dāng)前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
DMA INTERFACE
The SIO isdesigned tointerface to the 68000 family
DMA’sas a 68000 compatible device, using the cy-
cle steal mode. The SIO provides four outputs
(TxRDYA, RxRDYA, TxRDYB, RxRDYB) for re-
questingservicefromtheDMA.The SIOissuesare-
questforservice bypulsingthe RDYpinlowfor three
clock(CLK) cycles(see figure 4). TxRDY(when en-
abled) will be active when the transmit buffer be-
comesempty. RxRDY(whenenabled) willbe active
when a character is available in the receive buffer.
If Receive Interrupt On First Character Only is en-
abledduring aDMAoperation and aspecial receive
condition is detected, the RxRDY pin will not be-
comeactive. Instead, a special receive condition in-
terrupt will be generated by the channel.
RESET
There are two ways of resetting theSIO : an indivi-
dual, programmable channel reset and an external
hardware reset.
The individual channel reset is generated by writing
”18H” to the Command Register for the channel se-
lected. All outputs associated with the channel are
resethigh,TxCand RxCareinputs, SYNCisanout-
put, andTxDisforced marking. All R/Wregisters for
the channel areresetto”00H”, except thevector re-
gisterand the data register, which are not affected.
Readonlystatusregister 1isreset to”01H”(All Sent
set). Break/Abort, Interrupt Pending, and Rx Char-
acterAvailable bitsin read only status register 0 are
reset ; Underrun/EOM, Hunt/Sync, and Tx Buffer
Emptyare set ; CTS and DCD bits are setto the in-
vertedstate of their respective inputpins. Any inter-
ruptspending forthechannel arereset (anypending
interrupts in the other channel will not be affected).
Anexternalhardware resetoccurswhenthe RESET
pin is driven low for at least one clock (CLK) cycle.
Both channels are reset as listed above, and the
vector register is reset to ”0FH”.
ARCHITECTURE
The MK68564 SIO contains two independent, full-
duplexchannels. Each channel containsa transmit-
ter, receiver, modem control logic, interrupt control
logic, a baud rate generator, ten Read/Write regis-
ters,and two read only statusregisters. Each chan-
nelcan communicate with the busmasterusingpol-
ling, interrupts, DMA, or any combination of these
three techniques. Each channel also has the ability
toconnect thetransmitteroutput intothereceiverwi-
thout disturbing any external hardware.
Register Set
. The register set is the heart of each
channel. A channel is configured for different
communication protocols and interface options by
programming the registers. Table 1 lists all the re-
gisters available in the SIO and their addresses.
Data Register
. The Data Register is composed of
two separate registers : a write only register, which
is the Transmit Buffer, and a read only register,
which is the Receive Buffer. The Receive Buffer is
also the top register of a three register stack called
the receive data FIFO.
Vector Register
. The Vector Register is different
from the other 24 registers, because it may be ac-
cessed through eitherChannel A or Channel B du-
ring a R/W cycle.Duringan Interrupt Acknowledge
cycle, the contents of the Vector Register are pas-
sedtotheCPUtobe usedasapointer toaninterrupt
serviceroutine. IftheStatusAffectsVectorbit isLow
in the Interrupt Control Register, any data written to
the Vector Register will be returned unmodified du-
ringa Read Cycleoran IACK cycle. If the Status Af-
fects Vector bit is High, the lower three bits of the
vectorreturned during aRead orIACKcyclearemo-
dified toreflect the highest priority interrupt pending
in the SIO at that time. The upper five bits written to
theVector Register areunaffected. Afterahardware
reset only, this register contains a ”0FH” value,
whichisthe MK68000’s uninitialized interrupt vector
assignment.
MK68564
6/46
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK68901 | Multifunction Peripheral(多功能外圍電路) |
| MK70110 | Bluetooth? Module |
| MK70120 | Bluetooth? Module |
| ML2003IQ | Logarithmic Gain/Attenuator |
| ML2003CP | Logarithmic Gain/Attenuator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK68564N-04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68564N-05 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68564Q-04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68564Q-05 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68590P | 制造商:STMicroelectronics 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。