參數(shù)資料
型號(hào)： MK68564
廠商： 意法半導(dǎo)體
英文描述： Serial Input Output(串行I/O(雙通道,多功能外圍電路))
中文描述： 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路））
文件頁(yè)數(shù)： 11/46頁(yè)
文件大?。?/td> 464K
代理商： MK68564
in the data stream. Note that the CRC generator re-
sult (frame check) for SDLC data is also routed
through the zero insertion logic.
I/O CAPABILITIES
The SIOoffers the choice of Polling, Interrupt (vec-
toredornon-vectored), and DMATransfermodesto
transfer data, status, and control information to and
from the CPU or other bus master.
Polling
. ThePolled mode avoids interrupts. Status
Registers 0 and 1 are updated at appropriate times
for each function being performed (for example,
CRC Error status valid at the end of themessage).
All the interrupt modesof the SIO must be
disabled to operate the device in a polled environ-
ment.
While initsPollingsequence, theCPUexaminesthe
statuscontained inStatus Register 0 for each chan-
nel. The state of the status bits in Status Register 0
servesas an acknowledge to thePoll inquiry. Status
bitsD0and D2 indicatethat a receive ortransmitda-
ta transfer is needed. The rest of the status bits in
Status Register 0 indicate special statusconditions.
The receiver error condition bits in Status Register
1 donothaveto be readuntil the RxCharacter Avai-
lablestatus bit in Status Register 0 isset to a one.
Interrupts
. The SIO offers an elaborate interrupt
scheme to provide fast interrupt response in real-
time applications. The interrupt vector points to an
interrupt service routine in the memory. To service
operations inboth channels and to eliminate thene-
cessity of writinga statusanalysis routine (as requi-
redfora polling scheme), theSIO canmodify thein-
terrupt vector soitpoints to oneofeight interrupt ser-
viceroutines. Thisis done under program control by
setting the Status Affects Vector bit in the Interrupt
Control Registerofchannel Aorchannel B,toaone.
When this bit is set, the interrupt vector is modified
according to the assigned priority of the various in-
terrupting conditions.
Note: If theStatusAffects Vector bit is set in either
channel, the vector is modified for both channels.
Thisis the onlycontrol bit that operates inthis man-
ner in the SIO.
Transmit interrupts, Receive interrupts, and Exter-
nal/Status interrupts are the sources of interrupts.
Each interrupt source is enabled under program
control with Channel Ahaving a higher priority than
Channel B, and with Receiver, Transmitter, and Ex-
ternal/Status interrupts prioritizedin thatorder within
each channel. When the Transmit interrupt is en-
abled, theCPU is interrupted by the transmit buffer
becoming empty. This implies that the transmitter
must have had a data character written into it so t
canbecomeempty.When enabled, thereceiver can
interrupt the CPU in one of three ways :
Interrupt On First Character Only
Interrupt On All Receive Characters
Interrupt On A Special Receive Condition.
Interrupt On First Character Only
.This mode is
normally used to start a software Polling loop or a
DMA transfer routine using the RxRDY pin. In this
mode, the SIO generates an interrupt on the first
character received after this mode is selected and,
thereafter, only generates an interrupt if a Special
Receive Condition occurs. The Special Receive
Conditions that can cause an interrupt in this mode
are : Rx Overrun Error, Framing Error (in Asynchro-
nous modes), and End Of Frame (in SDLC mode).
Thismode isreinitialized by the Enable Interrupt On
Next Rx Character command. If a Special Receive
Condition interrupt occursin this interrupt mode,the
data with the special condition is heldin thereceive
data FIFO until an Error Reset Command isissued.
InterruptOnAllReceiveCharacters
.Inthismode,
an interrupt is generated whenever thereceive data
FIFO contains a character or a Special Receive
Condition occurs. The Special Receive Conditions
that can cause an interrupt in thismode are :Rx O-
verrun Error, Framing Error (in Asynchronous
modes), End of Frame (in SDLC mode), and Parity
Error (if selected).
Interrupt On A Special Receive Condition
. The
Special Receive Condition interrupt is not, as such,
a separate interrupt mode. Before a Special Re-
ceiveCondition cancause aninterrupt, eithertheIn-
terrupt On First Character Only or Interrupt On All
Receive Characters mode must be selected. The
Special Receive Condition interrupt will modify the
receive interrupt vectorifStatusAffectsVector isen-
abled.The Special Receive Condition status is dis-
played in the upper four bits of Status Register 1.
Two of the conditions causing a special receive in-
terrupt arelatchedwhentheyoccur;theyare:Parity
Error and Rx Overrun Error. These status bits may
onlybereset by an Error Reset command. When ei-
ther of these conditions occur, a read of StatusRe-
gister 1 will reflect any errorsin the current word in
the receive buffer plus any parity or overrun errors
sincethe last Error Reset command was issued.
External/Status Interrupts
. The main function of
the External/Status interrupt is to monitor the signal
transitions of the CTS, DCD,and SYNC pins ; how-
ever, an External/Status interrupt is also caused by
a TransmitUnderrun condition orby thedetectionof
a Break (Asynchronous mode) or Abort (SDLC
mode)sequence inthereceived datastream.When
any one of the above conditions occur, the exter-
MK68564
11/46
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