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參數(shù)資料
| 型號： | MK68564 |
| 廠商： | 意法半導體 |
| 英文描述： | Serial Input Output(串行I/O(雙通道,多功能外圍電路)) |
| 中文描述： | 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路）） |
| 文件頁數(shù)： | 19/46頁 |
| 文件大小： | 464K |
| 代理商： | MK68564 |
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Data Transfer
. A Transmit Interrupt is generated
each time the transmit buffer becomes empty. The
interrupt may be satisfied either by writing another
character into the transmit buffer or by resetting the
Transmit Interrupt Pending latch witha ResetTx In-
terrupt Pending command. Ifthe interrupt issatisfied
with this command, and nothing more is written into
the transmit buffer, there canbe nofurther Transmit
Interruptsdue to a Buffer Empty condition, because
it is the process of the buffer becoming empty that
causes the interrupts. This situation does cause a
Transmit Underrun condition when the data in the
shift register is shifted out.
Another way of detecting when the transmitter re-
quiresserviceistopoll theTxBufferEmptybitinSta-
tus Register0. This bit isset to a one every time the
data in the transmit buffer is downloaded into the
transmit shift register. When data is written to the
transmit buffer, this bit is reset to zero.
The SIOhas all the signals and controls necessary
to implement a DMA transfer routine for the trans-
mitter.The routine may be configured to enable the
DMA controller, after the first character is written to
the transmit buffer, and then using the TxRDY out-
put pin to signal the DMA that the transmitter re-
quires service. If a data character is notloaded into
the transmit buffer by the time the transmit shift re-
gisteris empty, the SIOenters the Transmit Under-
run condition.
Transmit Underrun/End of Message
. When the
transmitter has no further data to transmit, the SIO
insertsfiller characters to maintain synchronization.
TheSIOhastwoprogrammable optionsforhandling
this situation : sync characters can be inserted, or
the CRC characters generated so far can be sent,
followedbysynccharacters. Theseoptionsarecon-
trolled by the state of the Transmit Underrun/EOM
Latchin Status Register 0.
Following a hardware or softwarereset, the Trans-
mit Underrun/EOM Latch is setto aone.Thisallows
synccharacters to beinsertedwhenthereisnodata
to send. CRC is not calculated on theautomatically
inserted sync characters. To allowCRC
characters to be sent when the transmitter has no
data,the TransmitUnderrun/EOM Latchmustbere-
set tozero. This latch isreset by issuing a Reset Tx
Underrun/EOM Latch command in the Command
Register. Following the CRC characters, the SIO
sends sync characters to terminate the message.
There is no restriction as to when, in the message,
theTransmit Underrun/EOM Latch canbereset, but
once the reset command is issued, the 16-bitCRC
issentand followedby synccharacters thefirsttime
the transmitter has no data to send. A Transmit Un-
derruncondition willcausean External/Status Inter-
ruptto be generated whenever the Transmit Under-
run/EOM Latch is set.
For sync character insertion only, at thetermination
ofamessage, a TransmitInterruptisgenerated only
after the first automatically inserted sync character
is loaded into the transmit shift register. The status
bits in Status Register 0 indicate that the Transmit
Underrun/EOM Latch and the Tx Buffer Empty bit
are set.
For CRC insertion, followed by sync characters, at
the termination of a message, the Transmit Under-
run/EOM Latch is set, and the Tx Buffer Empty bit
is reset while the CRC characters are being sent.
When the CRCcharacters are completely transmit-
ted, the Tx Buffer Empty status bit is set, and a
Transmit Interrupt is generated, indicating to the
CPU that another message can begin. This Trans-
mit Interrupt occurs when the first sync character
following the CRC characters is loaded into the
transmit shift register. If no more messages are to
betransmitted,theprogram canterminatetransmis-
sion by disabling thetransmitter.
CRC Generation
. Setting the Tx CRC Enable bit in
the Transmit Control Register initiates CRC accu-
mulation when the program sends the first data
character to the SIO. To ensure CRC is calculated
correctly oneach message, theReset Tx CRCGen-
erator command should be issued before the first
data character of the message is sentto theSIO.
The Tx CRC Enable bit can be changed on the fly
at any point in the message to include or exclude a
particular data character from CRC accumulation.
The Tx CRC Enable bit should be in the desired
state when the data character is loaded from the
transmit data buffer into the transmit shift register.
To ensure this bit is in the proper state, the TxCRC
Enable bitshould beloaded before sending thedata
character to the SIO.
TransmitTermination
. The SIO isequipped with a
special termination feature that maintains datainte-
grityandvalidity. Ifthe transmitter is disabled(byre-
setting theTransmit Enable bit or using the TxAuto
Enable signal) while a data or sync character is
beingtransmitted, thecharacter is transmitted as u-
sualbut isfollowed by amarking line insteadof sync
or CRC characters. When the transmitter is disa-
bled,acharacter inthetransmit buffer remainsinthe
buffer. If the transmitter isdisabled while CRC char-
acters arebeingtransmitted, the16-bit transmission
is completed, but the remaining bits of the CRC
characters are replaced by sync characters.
MK68564
19/46
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相關代理商/技術參數(shù) |
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| MK68564N-04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
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| MK68564Q-04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68564Q-05 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68590P | 制造商:STMicroelectronics 功能描述: |
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