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參數(shù)資料
| 型號(hào)： | MK68564 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Serial Input Output(串行I/O(雙通道,多功能外圍電路)) |
| 中文描述： | 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路）） |
| 文件頁數(shù)： | 24/46頁 |
| 文件大?。?/td> | 464K |
| 代理商： | MK68564 |
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morebitstosend.Itdoes thisby firstsending thetwo
bytes of CRC and the following these with one or
more flags. This technique allows very high-speed
transmissionunder DMAorCPU control, withoutre-
quiring the CPU to respond quickly to the end of
message situation.
The action that theSIO takes in the underrun situa-
tion depends on the state of the Transmit Under-
run/EOM status bit in statusRegister 0. Following a
reset,theTransmit Underrun/EOM bitissettoaone
and preventstheinsertion ofCRC characters during
thetimethere is no datatosend. Consequently, flag
characters are sent. If the Transmit Underrun/EOM
status bit is zero when the underrun condition oc-
curs, the 16-bit CRC character is sent, followed by
one or more flag characters. The Transmit Under-
run/EOM bit is reset to zero by issuing the Reset Tx
Underrun/EOM Latch command in the Command
Register.
TheSIObegins tosend aframe whendataiswritten
into the transmit buffer. Between the time the first
data byte is written and the end of the message,the
Reset Tx Underrun/EOM Latch command must be
issued. The Transmit Underrun/EOM status bit will
then be in the reset state at the end of the message
(when underrun occurs), and CRC characters will
automatically be sent. The transmission of the first
CRC bit set the Transmit Underrun/EOM status bit
to a one and generates anExternal/Status interrupt.
Also, while CRC is being sent, the Tx Buffer Empty
bit in Status Register 0 is reset to indicate that the
transmitshift register isfullofCRCdata. When CRC
has been completely sent, theTx Buffer Empty sta-
tus bit is set,and a Transmit Interrupt is generated
toindicate thatanothermessagemaybegin. Thisin-
terrupt occurs because CRC has been sent, and a
flag has been loaded into the shift register. If no
moremessages aretobesent,the program canter-
minate transmission by disabling the transmitter.
Althoughthereisno restriction astowhenthe Trans-
mit Underrun/EOM bit can be reset within a mes-
sage,it isusually reset after the first data character
(secondary address field) is sent to theSIO.By re-
setting the status bit early in themessage, the CPU
has additional time (16 bits of CRC) to recognize if
an unintentional transmit underrun situation has oc-
cured and to respond with an Abort command. Is-
suingtheAbort commandstopstheflagsfromgoing
ontheline prematurely andeliminatesthepossibility
of the receiver accepting the frame as valid data.
Thissituation canhappen if, atthereceivingend, the
data pattern immediately preceding the automatic
flag insertion matches the CRC checker, giving a
false CRC check result.
CRC Generation
. The CRC generator must be re-
setto allones at the beginning ofeach frame before
CRC accumulation can begin.Actual accumulation
beginsonthefirstdata character (address field)loa-
ded intothe transmit buffer. The Tx CRCEnable bit
in the Transmit Control Register should be set to a
onebeforethefirstcharacter isloaded intothetrans-
mit buffer. In SDLC mode, all characters between
the opening and the closing flags are included in
CRCaccumulation. The outputofte CRCgenerator
is inverted before it is transmitted.
Transmit Termination
. The normal sequence at
the end of a frameis
A Transmit Interruptoccurs when thelast datachar-
acterwritten to thetransmit buffer isdownloaded in-
to the transmit shift register. This interrupt may be
cleared by issuing a Reset Tx Interrupt Pending
command.
AnExternal/Status Interruptoccurswhenthe firstbit
of the CRC character is transmitted. This interrupt
condition should first be testedto seeif theinterrupt
was causedby theTxUnderrun/EOM bitgoing High
andthenresetbyissuingaResetExternal/Status In-
terrupts command.
A Transmit Interrupt occurs when the first bit of the
flagis transmitted. Thisinterrupt may becleared by
issuing a Reset Tx Interrupt Pending command, by
loading the first character of the next message, or
by disabling the transmitter.
If the transmitter is disabled while a character is
beingsent, that character (data orflag) issentinthe
normal fashion but is followed by a marking line ra-
therthan CRC ormoreflagcharacters. If CRCchar-
acters are being sent at the time the transmitter is
disabled, all 16 bits will be transmitted, followedby
a marking line ; however, flags are sent in place of
CRC. Acharacter in the buffer when the transmitter
is disabled remains in the buffer.
SDLC RECEIVE
Initialization
. The receiver is enabled only after all
of the receive parameters are initialized. After the
ReceiverEnablebit intheReceiverControlRegister
is set toa one,the receiverwill be in theHunt phase
and will remain in this phase until the first flag is re-
ceived. While inthe SDLC mode,the receiver never
re-enters the Hunt phase, unless specifically in-
structed to do so by the program or when an Abort
character is detected in theincoming data stream.
MK68564
24/46
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| MK68564N-04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
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