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參數(shù)資料
| 型號(hào)： | MK68564 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Serial Input Output(串行I/O(雙通道,多功能外圍電路)) |
| 中文描述： | 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路）） |
| 文件頁數(shù)： | 4/46頁 |
| 文件大?。?/td> | 464K |
| 代理商： | MK68564 |
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SIO SYSTEM INTERFACE
INTRODUCTION
The MK68564 SIO is designed for simple and effi-
cientinterface to a MK68000 CPU system. All data
transfers between the SIO and the CPU are asyn-
chronous to the system clock. The SIO system
timing is derived from the chip select input (CS)du-
ringnormal read and writesequences, and from the
interrupt acknowledge input (IACK) during an ex-
ception processing sequence. CS is a function of
address decode and (normally) lower data strobe
(LDS). IACKis afunction oftheinterrupt levelonad-
dress lines A1, A2, and A3, an interrupt acknow-
ledgefunction code (FC0-FC2), and LDS.
Note : CS and IACK can never be asserted at the
sametime.
Note: Unusedinputs should bepulled up or down,
but never left floating.
READSEQUENCE
TheSIOwillbegin a read cycleif,onthefalling edge
of CS, the read-write (R/W) pin is high. The SIO will
respond by decoding the address bus (A1-A5) for
the register selected, by placing thecontents of that
register onthedatabuspins (D0-D7),and bydriving
the data transfer acknowledge (DTACK) pin low. If
theregister selected isnot implemented onthe SIO,
the data bus pins will be driven high, and then
DTACK will be asserted. When the CPUhas acqui-
red the data, the CS signal is driven high, at which
time the SIOwill drive DTACK high and thenthree-
state DTACK and D0-D7.
WRITESEQUENCE
TheSIOwillbeginawrite cycleif, onthefalling edge
of CS, the R/W pin is low. The SIO will respond by
latching the data bus, by decoding the address bus
for theregister selected, by loading theregister with
the contents of the data bus,and by driving DTACK
low. When the CPU hasfinished the cycle, the CS
input is driven high. At this time, the SIO will drive
DTACK high and will then three-state DTACK. If the
register selectedis notimplemented on the SIO,the
normal write sequence will proceed, but the data
bus contents will not be stored.
INTERRUPT SEQUENCE
The SIO is designed to operate asan independent,
interrupting peripheral, or, when interconnected
with other components, an interrupt priority daisy
chain can be formed.
Independent Operation
. Independent operation
requires that the interrupt enable in pin (IEI) be
connected to ground. The SIO starts the interrupt
sequence bydrivingtheinterrupt requestpin (INTR)
low. The CPUresponds to the interrupt by starting
an interrupt acknowledge cycle, in which the SIO
IACKpin isdriven low. The highest priority interrupt
request intheSIO,atthetimeIACKgoeslow,places
itsvectoronthe data bus pins.The SIO releasesthe
INTRpinanddrivesDTACKlow.WhentheCPUhas
acquired the vector, the IACK signal is driven high.
The SIO responds by driving DTACK to a high level
and then three-stating DTACK and D0-D7. If more
than one interrupt request is pending at the start of
an interrupt acknowledge sequence, the SIO will
drive the INTR pin low following the completion of
the interrupt acknowledge cycle. This sequence will
continue until all pending interrupts are cleared. If
the SIO is not requesting an interrupt when IACK
goeslow,theSIOwillnotrespond totheIACKsignal
; DTACK and the data bus will remain three-stated.
DaisyChainOperation
. Theinterrupt priority chain
is formed by connecting the interrupt enable out pin
(IEO)of a higher priority part to IEI ofthe next lower
priority part. The highest priority part in the chain
shouldhave IEI tied to ground. The Daisy Chaining
capability (figures 2 and 3) requires that all partsin
a chain have a common IACK signal. When the
commonIACK goes low, allparts freeze and priori-
tize interrupts in parallel. Then priority is passed
down the chain, via IEI and IEO, until a part which
has a pending interrupt, once IEI goes low, passes
a vector, does not propagate IEO, and generates
DTACK.
The state of the IEI pin does not affect the SIO in-
terrupt control logic. The SIOcan generate an inter-
ruptrequest any timeitsinterrupts areenabled. The
IEO pin is normally high ; it will only go low during
anIACKcycleifIEIislow andnointerrupt ispending
intheSIO.The IEOpin willbe forced high whenever
IACKor IEI goes high.
MK68564
4/46
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