- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377968 > MK68564 (意法半導(dǎo)體) Serial Input Output(串行I/O(雙通道,多功能外圍電路)) PDF資料下載
參數(shù)資料
| 型號： | MK68564 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Serial Input Output(串行I/O(雙通道,多功能外圍電路)) |
| 中文描述： | 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路）） |
| 文件頁數(shù)： | 31/46頁 |
| 文件大?。?/td> | 464K |
| 代理商： | MK68564 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
D3 : Receiver CRC Enable
This bit, when set to a one in a Synchronous mode
other than SDLC, is usedto initiate CRCcalculation
at thebeginning of thelastbyte transferred from the
receiver shift register to the receive data FIFO. This
operation occurs independently of the number of
bytes in the receive data FIFO. As long as this bit is
set, CRC willbe calculated on all characters recei-
ved (data or sync). When a particular byte is to be
excludedfromCRCcalculation, thisbitshould be re-
set to a zero before the next byte is transferred to
the receive data FIFO. If this featureis used, care-
mustbetakentoensurethateight bits percharacter
are selected inthe reciever because of an inherent
eight-bit delay from the receiver shift register to the
CRC checker.
Whenthisbit is set to a onein SDLCmode, the SIO
will calculate CRC on all bits between the opening
andclosingflags.Thereisnodelay fromthereceiver
shift register to the CRC checker in SDLC mode.
This bit is ignored inAsynchronous modes.
D2 : Address Search Mode
Setting this bit to a one in SDLC mode forces the
comparison of thefirstnon-flag character of aframe
with the address programmed in Sync Word Regis-
ter 1 or the global address (11111111). If a match
does not occur, the frame is ignored, and the recei-
verremains idle untilthe next frame is detected. No
receiver interrupts can occur in this mode, unless
there is an address match. This bit is ignored in all
modes exceptSDLC.
D1 : Sync Character Load Inhibit
When this bit is set to a one in any Synchronous
mode except SDLC, the SIOcompares the byte in
SyncWord Register 1 with the byteabout to be loa-
ded into the receiver data FIFO. If the twobytes are
equal,the loadis inhibited, and noreceiver interrupt
willbegenerated bythischaracter. CRC calculation
is performed on all bytes, whether they are loaded
into the data FIFOor not, when the receiver CRC is
enabled. Note that the register used in the compa-
rison contains thetransmit sync character in Mono-
syncand External syncmodes. Thisbit isignored in
SDLC mode because all flag characters are auto-
matically striped in this mode without performing
CRC calculations on them.
If thisbitis settoa one inAsynchronous modes,any
character received matching the contents of Sync
Word Register 1 will not be loaded into the receive
data FIFO,and no receiver interrupt will be genera-
ted for the character.
D0 : Receiver Enable
When this bit is set to a one, receiver operation be-
gins if Rx Auto Enables mode is not selected. This
bit should be set only after all receiver parameters
are established, and the receiver is completely ini-
tialized.When thisbitiszero,thereceiver isdisabled
; the receiverCRCchecker isreset,and thereceiver
is inthe Huntmode.
TRANSMITTER CONTROL REGISTER
(XMTCTL)
This register contains the control bits and parame-
ters for the transmitter logic. Thisregister isreset to
”00H” by a channel or hardware reset.
D7, D6 Transmit Bits/Character 1 and 0
The state of thesetwo bits determine the number of
bitsin each byte transferred fromthe transmitbuffer
to the transmit shift register. All data written to the
transmit buffer must be right-justified with the least-
significant bits first. The Five Or Less mode allows
transmission of one to fivebits per character ; how-
ever, the CPU should format the data characters as
shown. If Parity is enabled, one additional bit per
character will be transmitted.
D7
TX
BITS
CHAR 1
D6
TX
BITS
CHAR 0
D5
TX
AUTO
ENABLES
D4
SEND
BREAK
D3
TX
CRC
ENABLE
D2
DTR
D1
RTS
D0
TX
ENABLE
TX BITS/
CHAR 1
0
0
1
1
TX BITS/
CHAR 0
0
1
0
1
Bits/character
(no parity)
Five or Less
6
7
8
D7 D6 D5 D4 D3 D2 D1 D0
1
1
1
1
0
Five or Less
Sends One Data Bit
Sends Two Data
Bits
Sends Three Data
Bits
Sends Four Data
Bits
Sends Five Data
Bits
1
1
0
1
1
0
0
1
0
0
0
1
0
0
D
0
0
0
D
D
0
0
D
D
D
0
D
D
D
D
D
D
D
D
D
MK68564
31/46
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK68901 | Multifunction Peripheral(多功能外圍電路) |
| MK70110 | Bluetooth? Module |
| MK70120 | Bluetooth? Module |
| ML2003IQ | Logarithmic Gain/Attenuator |
| ML2003CP | Logarithmic Gain/Attenuator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK68564N-04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68564N-05 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68564Q-04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68564Q-05 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68590P | 制造商:STMicroelectronics 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。