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參數(shù)資料
| 型號： | MK68564 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Serial Input Output(串行I/O(雙通道,多功能外圍電路)) |
| 中文描述： | 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路）） |
| 文件頁數(shù)： | 25/46頁 |
| 文件大?。?/td> | 464K |
| 代理商： | MK68564 |
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Receiver Characteristics
. The receiver may be
programmed to assemble five to eight data bitsinto
a character. The character is right-justified in the
shift register and transferred to thereceive data FI-
FO. Alldatatransferstothe FIFOarein8-bitgroups.
Whenthecharacter lengthprogrammed islessthan
eight bits, the most significant bit(s) transferred with
a character, will be the least-significant bit(s) of the
next character. The character length programmed
may be changed on the fly during the reception of a
frame ; however, care must be taken to assure that
the change is effective, before the number of bits
specified for thecharacter length has been assem-
bled.
The address field in the SDLC frame is defined as
an 8-bit field. When theAddress Search Modeisse-
lected, the receiver will compare the 8-bit character
following the flag (first non-flag character) against
the address programmed in Sync Word Register 1
or the hardwired global address (11111111). When
the address field of the SDLC frame matches either
address, data transfer will begin with the address
character being loaded into the receive data FIFO.
If the frame address does not match either address,
the receiver will remain idle and continue checking
everyframe received for anaddress match. Thead-
dress comparison is always done on the first eight
bits following a flag, regardless of thebits per char-
acter programmed.
The SIO receiver is capable of matching only one
address character. Once a matchoccurs, all data is
transferred to thereceive dataFIFOat theprogram-
med bits per character rate. If SDLC extended ad-
dressfield recognition isused (two or more address
characters), the CPU program must be capable of
determining whetheror nottheframehas a correct
address field. If thecorrect address fieldisnotrecei-
ved, the Hunt bit can be set to suspend reception
and start searching for the next frame. The control
field of an SDLC frame is transparent to the SIO ; it
is transferred to the data FIFO as a data character.
All extra zeros, inserted in the data stream by the
transmitter, are automatically deleted in the recei-
ver.
Data Transfer and Status Monitoring.
After re-
ceipt of a valid flag, the assembled characters are
transferred to thereceive data FIFO, and the status
information for each character is transferred to the
receive error FIFO. The following four modes are
available to transfer thereceived data and its asso-
ciated statusto the CPU.
No Receiver Interrupts Enabled
. Thismode is u-
sed for polling operations or for off-line conditions.
When transferring data, using a polling routine, the
Rx Character Available bit in Status Register 0
shouldbechecked todetermine whether ornotare-
ceivecharacter is available for transfer. Only when
a character is available should the receive buffer
and Status Register 1 be read. The Rx Character
Available bit is set to a one every time a character
is shifted to the top of the receive data FIFO. This
bit is reset when the receive buffer is read.
Interrupt On First Character Only
. This interrupt
modeis normally used to start a DMA transfer rou-
tine, or in some cases, a polling loop. The SIO will
generate an interruptthefirsttimeacharacterisshif-
ted to the top of the receive data FIFO after this
modeis selected or reinitialized. An interrupt willbe
generated thereafter only if a Special Receive
Condition isdetected. Thismode is reinitialized with
the Enable Interrupt On Next Received Character
command. Parity Errors do not cause interrupts in
this mode, but a Receive Overrun Error or an End
Of Frame condition will.
InterruptOnEvery Character
. This interrupt mode
willgenerate a Receiver Interrupt every time a char-
acter is shifted to the top of the receive data FIFO.
A SpecialReceiveCondition interrupt onaParity er-
ror is optional in this mode.
Special Receive Condition Interrupt
. The special
condition interrupt mode isnotaninterrupt mode, as
such, but works in conjunction with Interrupt On E-
veryCharacter or Interrupt On First Character Only
modes. When the Status Affects Vector bit ineither
channel is set, aSpecial Receive Condition will mo-
dify the Receive Interrupt vector to signal the CPU
of thespecial condition. Receive Overrun Error, Pa-
rityError,andEnd OfFramearetheSpecialReceive
Conditions inSDLC mode. The Overrun and Parity
error status bits in Status Register 1 are latched
when they occur ; the End Of Frame bit is not lat-
ched. The two bits that are latched will remain lat-
chedand will generate a Special Receive Condition
Interrupt at every character available time until an
Error Reset command is issued. Since the two sta-
tusbits arelatched, theerror status inStatus Regis-
ter 1, when read, will reflect an error in the current
word in the receive buffer, in addition to any Parity
orOverrunerrors receivedsince thelastErrorReset
command.
SDLC Receive CRC Checking
. Control of the re-
ceiver CRC checker is automatic. It is reset by the
leading flag, and CRC is calculated up to the final
flag. The byte that has the End Of Frame bit set is
the byte that contains the result of the CRC check.
If the CRC/Framing Error bit is not set (zero), the
CRC indicates a validreceived message. A special
check sequence is used for the SDLC check, be-
MK68564
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| MK68564N-04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
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