參數(shù)資料
型號(hào)： MK68564
廠商： 意法半導(dǎo)體
英文描述： Serial Input Output(串行I/O(雙通道,多功能外圍電路))
中文描述： 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路））
文件頁(yè)數(shù)： 28/46頁(yè)
文件大?。?/td> 464K
代理商： MK68564
D5, D4 : Sync Modes 1 and 0
These bits select the various options for character
synchronization. These bits are ignored, unless
Sync modes is selected in theStop Bits filed of this
register.
D3, D2 : Stop Bits 1 and 0
Thesebits determine the number of stopbitsadded
to each Asynchronous character that is transmitted.
The receiver always checksforone stopbit in Asyn-
chronous mode. A special code (00) signifies that a
Synchronous mode isto beselected. 1 1/2 stopbits
is not allowed ifx1 clock rate is selected, because it
willlock up the transmitter.
D1 : Parity Even/Odd
If theParity Enable bitisset,thisbitdetermines whe-
therparity is checked as even or as odd. (1 = even,
0 = odd). This bit is ignored if the Parity Enable bit
is reset.
D0 : Parity Enable
If this bit is set to a one, one additional bit position
beyond those specified in thebits/character control
fieldisadded tothetransmitteddata andisexpected
in the receive data. The received parity bit is trans-
ferredto the CPU as part of the data character, un-
lesseight bits percharacter isselected intheRecei-
ver Control Register.
INTERRUPT CONTROL REGISTER
(INTCTL)
Thisregister contains thecontrol bits forthe various
interrupt modes and the DMAhandshaking signals.
Thisregister is reset to ”00H” by a channel or hard-
ware reset.
D7 : CRC-16/SDLC-CRC
ThisbitselectstheCRCpolynomial usedbyboththe
transmitter and receiver. When set to a one, the
CRC-16 polynomial (x16 + x15 + x2 + 1) is used ;
when reset to a zero, the SDLC-CRC polynomial
(x16 + x12 + x5 + 1) is used. If the SDLC mode is
selected, theCRCgenerator andcheckerarepreset
to all ones and a special check sequence is used.
The SDLC-CRC polynomial must be selected in
SDLC mode. Failure to do so will result in receiver
CRCerrors. When a Synchronous mode,otherthan
SDLC, is selected, the CRC generator and checker
arepresettoallzeros(for bothpolynomials). This bit
must be programmed before CRC is enabled in the
receiver and transmitter control registers, to assure
valid CRCgeneration and checking.This bitisigno-
red inAsynchronous modes.
D6 : Tx Ready Enable
When this bit is set to a one, the TxRDYoutput pin
willpulse Lowfor threeclock cycles (CLK) when the
transmit buffer becomes empty. When this bitis ze-
ro, the TxRDY pinis heldHigh.
D5 : Rx Ready Enable
When this bit is set to a one, the TxRDYoutput pin
will pulse Low for three clockcycles (CLK) when a
character is available in thereceive buffer. If a Spe-
cial Receive Condition is detected when the Re-
ceive Interrupt On FIrst Character Only interrupt
mode is selected, the RxRDY pin will not become
active ; instead, a special Receive Condition inter-
rupt will be generated. When this bit is zero, the
RxRDY pin willbe held High
SYNC
MODE 1
0
0
1
SYNC
MODE 0
0
1
0
1
1
8-bit Programmed Sync
16-bit Programmed Sync
SDLC Mode (01111110 flag
pattern)
External Sync Mode
STOP
BIT 1
0
0
1
1
STOP
BIT 0
0
1
0
1
Sync Modes
1 Stop Bit per Character
11/2 Stop Bits per Character
2 Stop Bits per Character
D7
D 6
CTX
RDY
ENABLE
D5
D4
D3
D2
D 1
D0
CRC16/
SDLC
RX RDY
ENABLE
RX INT
MODE
1
RX INT
MODE
0
STATUS
AFFECTS
TX INT
ENABLE
EXT INT
ENABLE
CLOCK
RATE 1
0
0
CLOCK
0
1
1
1
0
1
x1
x16
x32
x64
Clock Rate = Data Rate
Clock Rate =16 x Data
Rate
Clock Rate =32 x Data
Rate
Clock Rate =64 x Data
Rate
MK68564
28/46
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