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參數(shù)資料
| 型號： | MK68564 |
| 廠商： | 意法半導體 |
| 英文描述： | Serial Input Output(串行I/O(雙通道,多功能外圍電路)) |
| 中文描述： | 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路）） |
| 文件頁數(shù)： | 34/46頁 |
| 文件大小： | 464K |
| 代理商： | MK68564 |
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SDLC.
D6 : CRC/Framing Error
In Asynchronous modes, ifa Framing Error occurs,
this bit is set to a one for the receive character in
which theframingerroroccurred. Whenthisbitisset
to a one, a Special Receive Condition interrupt will
be requested, if receiver interrupts are enabled.
DetectionofaFramingErroradds anadditional one-
half bit time to the character time, so that the Fra-
ming Error is not interpreted as a new start bit.
In Synchronous and SDLC modes, thisbit indicates
the result of comparing the received CRC value to
the appropriate check value. Azero indicates that a
match has occurred. This bit is usually set since
mostbit combinations result in anon-zero CRC,ex-
cept for a correctly completed message. Receiver
interrupts are not requested by theCRC Error bit.
The CRC/Framing bit is not latched in any receiver
mode.It is always updated when thenextcharacter
is received. AnError Reset command (command 6)
willalways reset this bit to zero.
D5 : Receive Overrun Error
This bit indicates that the receive data FIFOhas o-
verflowed. Only the character that has been written
over is flagged with this error. When the character
is read, the error condition is latched until reset by
the Error Reset command (command 6). If receiver
interruptsareenabled, the overrun character and all
subsequent characters received, until the Error Re-
set commandis issued, will generate a Special Re-
ceive Condition interrupt request.
D4 : Parity Error
When parity is enabled, this bit is set to a one for
those characters whose parity does not match the
programmed sense (even/odd). This bit is latched
so thatonce an error occurs, it remains set until the
ErrorReset command(command 6)is issued.If pa-
rityisa SpecialReceive Condition,a Parity isa Spe-
cial Receive Condition, a Parity Error will cause a
Special Receive Condition interrupt request on the
character containing theerrorandonallsubsequent
characters untilthe Error Resetcommand isissued.
D3, D2, D1 : Residue Codes 2, 1, and 0
Inthosecases oftheSDLCreceive mode,wherethe
I-field is not an integral multiple of the character
length, thesethree bits indicate the length of the re-
sidualI-fieldreadintheprevious bytes.These codes
are meaningful onlyforthe transfer inwhichtheEnd
Of Framebit isset.Thisfieldissetto 000 byachan-
nel or hardware reset and can leave this state only
if SDLC modeis selected, and a character is recei-
ved.
FOR EIGHT BITS PER CHARACTER
Ifareceivecharacter length, different fromeightbits,
is used for the I-field, a table similar to the previous
one maybe constructed for each differentcharacter
length. For no residue (that is, the last character
boundary coincides with the boundary of the I-field
and CRC field), the Residue codes are as follows :
D0 : All Sent
This bit is only active in Asynchronous modes ; itis
always High in Synchronous or SDLC modes. This
bitisLowwhilethetransmitter issending characters:
it will go High only after all the bits of the character
are transmitted, and thetransmit buffer is empty.
DATA REGISTER (DATARG)
The Data Register is actually two separate regis-
ters; a write onlyregister that is theTransmit Buffer,
and a read only register that is the Receiver Buffer.
TheReceiver Bufferisalsothetop register ofathree
Residue
Code 2
Residue
Code 1
Residue
Code 0
I-Field
Bits
In
Previous
Byte
0
0
0
0
0
0
1
2
I-Field
Bits
In Second
Previous
Byte
3
4
5
6
7
8
8
8
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
Bits Per Character Residue
Code 2
0
0
0
0
Residue
Code 1
1
0
1
0
Residue
Code 0
1
0
0
1
8 Bits Per Character
7 Bits Per Character
6 Bits Per Character
5 Bits Per Character
D7
D6
D5
D4
D3
D2
D1
D0
DATA
7
DATA
6
DATA
5
DATA
4
DATA
3
DATA
2
DATA
1
DATA
0
I-Fiel Bits are Right-justified in all Cases.
MK68564
34/46
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相關(guān)代理商/技術(shù)參數(shù) |
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| MK68564N-04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68564N-05 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68564Q-04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68564Q-05 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68590P | 制造商:STMicroelectronics 功能描述: |
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