參數(shù)資料
型號(hào)： MK68564
廠商： 意法半導(dǎo)體
英文描述： Serial Input Output(串行I/O(雙通道,多功能外圍電路))
中文描述： 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路））
文件頁(yè)數(shù)： 15/46頁(yè)
文件大小： 464K
代理商： MK68564
in the Transmitter Control Register may also be u-
sed to signal the end of transmission. If thisbit is set
to aone,itsassociatedoutput pin (RTS)willgoLow.
When this bit is reset to a zero, the RTS pin will go
Highone bit time after the transmit clock that clocks
outthelaststop bit,onlyifthetransmit bufferisemp-
ty.
The Transmit Data output (TxD) is held marking
(High) after a reset or when the transmitter has no
data to send. Under program control, the Send
Breakcommand canbe issuedto hold TxD spacing
(Low) until the command is cleared, even if the
transmitter is not enabled.
ASYNCHRONOUS RECEIVE
Asynchronous operation begins when the Receiver
Enablebit in the Receiver Control Register is set to
a one.If theRxAuto Enables bitisalso set, theData
Carrier Detect (DCD) input pin mustbeLow as well.
The receiver will start assembling a character as
soon as a valid start bit is detected, if a clock mode
other than x1 is selected. A valid start bit is a High-
to-Low transition on the Receive Data input (RxD)
with the Low time lasting at least one-half bit time.
TheHigh-to-Low transitionstartsaninternalcounter
and, at mid-bit time, the counter output is used to
sample the input signal to detect if it is still Low.
When this condition is satisfied, the following data
bits aresampled atmid-bit timeuntiltheentirechar-
acter is assembled. The start bit detection logic is
then rearmed to detect the next High-to-Low trans-
ition.Ifthex1 clockmode isselected,thestartbitde-
tection logic is disabled, and bit synchronization
must be accomplished externally. Receive data is
sampled on the rising edge of the Receiver Clock
(RxC).
The receiver may be programmed to assemble five
to eight data bits, plus a paritybit, into a character.
The character is right-justified in the shift register
andthentransferredtothe receive dataFIFO.All da-
ta transfers to theFIFOare ineight-bit groups. Ifthe
character length assembled is less than eight bits,
the receiver inserts ones in the unused bits. If parity
is enabled, theparity bit istransferred withthe char-
acter, unless eight bits per character is program-
med,inwhich case,the parity bitis stripped fromthe
character before transfer.
AReceiverInterrupt request isgenerated everytime
a character is shifted to the top of the receive data
FIFO, if Interrupt On All Receive Characters mode
isselected. TheRxCharacter Available bitinStatus
Register 0isalso settoaone everytimeacharacter
isshifted tothetop of thereceive data FIFO.TheRx
Character Available bit is reset to a zero when the
receive buffer is read.
Aftera character is received, itischecked forthe fol-
lowing error conditions :
Parity Error
. Ifparity is enabled, the Parity Errorbit
inStatus Register 1 issettoa onewhenever thepa-
rity bit of the received character does notmatch the
programmed parity. Once this bit is set, it remains
set (latched), until an Error Reset command
(Command 6) is issued. A Special Receive Condi-
tioninterrupt isgenerated whenthisbitisset,ifparity
is programmed as a Special Receive Condition.
Framing Error
. The CRC/Framing Error bit in Sta-
tus Register 1 is set to a one, if the character is as-
sembled withoutastopbit(aLowleveldetected ins-
teadofastopbit).Thisbitissetonly forthecharacter
on which the framing error occurred ; it is updated
at everycharacter time. Detection of aframing error
adds an additional one-half of a bit time to the char-
acter time,so the framing error is not interpreted as
a newstartbit. ASpecialReceiveCondition interrupt
is generated when this bit is set..
OverrunError
. If four or more characters arerecei-
ved before the CPU(or other busmaster) reads the
receive buffer, the fourth character assembled will
replace the thirdcharacter inthe receive dataFIFO.
If morethan four charactershave beenreceived,the
last character assembled will replace the thirdchar-
acter in the data FIFO. The character that has been
written over is flagged with an overrun error in the
error FIFO.
When this character is shifted to the top of the re-
ceive data FIFO, the Receive Overrun Error bit in
StatusRegister 1 is set to a one ; theerror bit is lat-
ched in the status register, and a Special Receive
Condition interrupt is generated. Like Parity Error,
this bit can only be reset by an Error Reset
Command.
Break Condition
. A break character is defined as
a start bit, an all zero data word, and a zero inplace
of the stop bit. When a break character is detected
in the receive data stream, the Break/Abort bit in
Status Register 0 is set to a one, and an Exter-
nal/Status interrupt is requested. This interrupt is
then followed by a Framing Error interrupt request
when the CRC/Framing Error bit inStatus Register
1 is set. A Reset External/Status Interrupts
command (Command 2) should be issued to reini-
tialize the break detection interrupt logic. The recei-
ver will monitor the data stream input for the termi-
nation of the break sequence. When this condition
is detected, the Break/Abort bit will be reset, if
MK68564
15/46
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