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參數(shù)資料
| 型號： | MK68564 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Serial Input Output(串行I/O(雙通道,多功能外圍電路)) |
| 中文描述： | 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路）） |
| 文件頁數(shù)： | 22/46頁 |
| 文件大?。?/td> | 464K |
| 代理商： | MK68564 |
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Figure 12 :
Transmit/Receive SDLC/HDLC Message Format.
sage length and bit patterns. The SIO has several
built-in features to handle variable message length.
Detailed information concerning SDLCprotocol can
befound inliteratureon thissubject,suchasIBMdo-
cument GA27-3093.
The SDLCmessage, called the frame(figure 12), is
opened and closedby flags, which are similar to the
sync characters used in other Synchronous proto-
cols. The SIO handles the transmission and reco-
gnition oftheflagcharacters thatmarkthebeginning
and end of the frame. Notethat the SIO can receive
shared-zero flags but cannot transmit them. The 8-
bit address field of a SDLC frame contains the se-
condary station address. The SIO receiver has an
Address Search mode, which recognizes the se-
condary station so that it can accept or reject a
frame.
The control field of the SDLC frame is transparent
to the SIO ; it is simply transferred to the CPU. The
SIOhandles the Frame Check sequence in a man-
ner that simplifies the program byincorporating fea-
tures such as initializing the CRC generator to all
ones,resetting the CRC checker when the opening
flagisdetectedinthereceive mode,andsending the
Frame Check/Flag sequence in the transmit mode.
Controller hardware is simplified by automatic zero
insertion and deletion logic, contained in the SIO.
To set upthe SIOfor SDLC operation, thefollowing
registers need to be initialized : Mode Control Re-
gister, Interrupt Control Register, Receiver Control
Register, Transmitter Control Register, Sync Word
Register 1, and Sync Word Register 2. The Mode
Control Register mustbeprogrammed before theo-
therregisters toassureproper operation of the SIO.
The following registers are used to transfer data or
communicate status between the SIO and the CPU
or other bus master when operating inSDLC mode
: Command Register, Status Register 0, Status Re-
gister1, DataRegister, and the Vector Register.
Sync Word Register 1 contains the secondary sta-
tion address, and Sync Word Register 2 storesthe
flag character and must be programmed
”01111110”.
The SIO provides four I/O lines in SDLC mode that
may be used for modem control, for external inter-
rupts, or as general purpose I/O. The Request To
Send (RTS) and Data Terminal Ready (DTR) pins
are outputs that followtheinverted stateoftheir res-
pective bits in the Transmit Control Register. The
Data Carrier Detect (DCD) and Clear To Send
(CTS) pins are inputs that can be used as auto en-
ablesto the receiver andtransmitter, respectively. If
External/Status Interrupts are enabled, the DCD
and CTS pins will be monitored for a change of sta-
tus.If these inputschange for a period of timegrea-
ter than the minimum specified pulse width, an in-
terrupt will be generated.
In the following discussion, all interrupt modes are
assumed enabled.
to
SDLC TRANSMIT
Initialization
. TheSIO is initialized for SDLC mode
by selecting these parameters in the Mode Control
Register : x1 Clock Mode, SDLC Mode, and Sync
ModesEnabled. Parityisnormally notused inSDLC
mode, because the transmitter will not add parity to
the flag character or the CRC characters, thuscau-
singParity Errors in thereceiver. If CRCisto becal-
culated on the transmitted data, the SDLC-CRC
polynomial mustbeselected in the Interrupt Control
Register (CRC-16 polynomial in SDLC Mode will
produce unknown results).
After reset (hardware or software), or when the
transmitter is not enabled, the Transmit Data (TxD)
output pin is held High (marking). Under program
control, the Send Break bit in the Transmit Control
Register can be setto a one, forcing the TxDoutput
toa Lowlevel(spacing), even ifthetransmitter isnot
enabled. The spacing condition willpersist until the
SendBreakbitisresettoazero.Ifthetransmitbuffer
is empty when the Transmit Enable bit is set to a
one, the transmitter will start sending flag charac-
ters.Continuous flagswillbe transmittedontheTxD
V000386
MK68564
22/46
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