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參數(shù)資料
| 型號： | MK68564 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Serial Input Output(串行I/O(雙通道,多功能外圍電路)) |
| 中文描述： | 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路）） |
| 文件頁數(shù)： | 32/46頁 |
| 文件大?。?/td> | 464K |
| 代理商： | MK68564 |
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D5 : Transmit Auto Enables
When this bit is set to a one, and theTransmit Ena-
ble bitisalsoset, a Lowon the CTSinput pinwillen-
able the transmitter. When this bit is zero, the CTS
pin issimply an input totheSIO,and itsstatusisdis-
played in Status Register 0.
D4 : Send Break
When set to a one, this bit immediately forces the
Transmit Data output pin (TxD) to a spacing condi-
tion (continuous 0’s), regardless of any data being
transmitted at the time. This bit functions, whether
the transmitter is enabled or not. When thisbitis re-
set to zero, the transmitter will continue to send the
contents of the transmit shift register. The shift re-
gistermaycontainsynccharacters,data characters,
or all ones.
D3 : Transmitter CRC Enable
This bit determines if CRC calculations are perfor-
med on a transmitted data character. If this bit is a
one at the timea character is loaded fromthe trans-
mit buffer to the transmit shift register, CRC is cal-
culated on thecharacter. CRC is not calculated on
any automatically inserted sync characters. CRC is
notautomatically appended totheendofamessage
unless this bit is set, and the Transmit Under-
run/EOMstatus bitinStatusRegister 0isresetwhen
a Transmit Underrun condition occurs. If thisbit is a
zero when a character is loaded from the transmit
buffer into the transmit shift register, no CRCcalcu-
lations are performed on the character. This bit is i-
gnored inAsynchronous modes.
D2 : Data Terminal Ready (DTR)
This is the control bit for the DTR output pin. When
this bit is set to a one,theDTRpin goes Low: when
this bit is reset to a zero, the DTR pin goes High.
D1 : Request To Send (RTS)
Thisis the controlbit for the RTS output pin. In Syn-
chronous modes, when this bit is set to a one, the
RTS pin goes Low ; when this bit is reset to a zero,
the RTS pin goes High. In Asynchronous modes,
when this bit is set, the RTS pin goes Low ; when
this bit is reset, the RTS pin will go High only after
allthe bitsof the character are transmitted, and the
transmit buffer is empty.
D0 : Transmitter Enable
Data is not transmitted until this bit is set to a one,
until the Send Break bit is reset and, if Tx Auto En-
ables mode is selected, until theCTSpin isLow.To
transmit sync or flag characters in Synchronous
modes, thisbithastobesetwhenthetransmitbuffer
is empty. Data or sync characters inthe process of
beingtransmittedare completely sent ifthisbitisre-
set to zero after transmission has started. If this bit
is reset during the transmission ofa CRC character,
sync or flag characters are sent instead of the CRC
character.
STATUS REGISTER 0 (STAT 0)
READ ONLY
This register contains the status of the receive and
transmit buffers and the status bits for the five
sources of External/Status interrupts.
D7 : Break/Abort
This bit is reset by a channel or hardware reset. In
Asynchronous modes, this bit is set when a Break
sequence (null character plus framing error) is de-
tectedinthereceived datastream. An External/Sta-
tus interrupt, if enabled, is generated when Break is
detected. The interrupt service routine mustissue a
Reset
External/Status
(Command 2) to the SIO, so the break detection lo-
gic can recognize the termination of the Break se-
quence.
The Break/Abort bit is reset to a zero when the ter-
minationofthe Break sequence isdetectedinthein-
coming data stream. The termination of the Break
sequence also causes the generation of an Exter-
nal/Status interrupt. Command 2 must be issued to
enable the break detection logic to look for the next
Breaksequence. Asingle extraneous null character
is present in the receiver after the termination of a
break; itshould be read and discarded.
In SDLC mode, this bit is set by thedetection of an
Abort sequence (seven or more ones) in the recei-
ved data stream. The External/Status Interrupt is
handled thesame way as in thecase of a Break se-
quence. The Break/Abort bit is notused intheother
Synchronous modes.
Interrupt
command
D6 : Transit Underrun/EOM
Thisbit issetto aone following a hardware or chan-
nel reset, when the transmitter is disabled or when
a Send Abort command (Command 1) is issued.
Thisbit canonlybe reset by the Reset Transmit Un-
derrun/EOM Latch command in theCommand Re-
gister. This bit is used to control the transmission of
D7
D6
D5
CTS HUNT/
D4
D3
DCD TX BUFR
EMPTY
D2
D1
D0
RX
CHAR
AVAIL
BREAK/
ABORT
UNDERRUN
/EOM
SYNC
INTERPT
PENDING
MK68564
32/46
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相關(guān)代理商/技術(shù)參數(shù) |
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| MK68564N-04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
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