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參數(shù)資料
| 型號： | MK68564 |
| 廠商： | 意法半導體 |
| 英文描述： | Serial Input Output(串行I/O(雙通道,多功能外圍電路)) |
| 中文描述： | 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路）） |
| 文件頁數(shù)： | 27/46頁 |
| 文件大小： | 464K |
| 代理商： | MK68564 |
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Command 0
(Null). The Null command has no ef-
fect on the MK68564 SIO.
Command 1
(Send Abort). This command is used
in SDLC mode to transmit a sequence of eight to
thirteen ones. This command always empties the
transmitbufferanssetstheTxUnderrun/EOM Latch
in StatusRegister 0 to a one
Command2
(Reset External/Status Interrupts)
.
Af-
ter an External/Status interrupt (a change on a mo-
dem line ora Break condition, for example), theup-
per five bits in Status Register 0 are latched. This
command reenables thesebitsandallowsinterrupts
to occur again as a result of a status change. Lat-
ching the statusbits captures short pulses, until the
CPU has time to read the change. This command
should be issued prior to enabling External/Status
Interrupts.
Command 3
(Channel Reset). This command di-
sables boththereceiverandtransmitter, forces TxD
to a marking state (”1”), forces the modem control
signals high, resets anypending interrupts from this
channel, andresetsallcontrolregisters.See theRe-
set section in the SIO System Interface Description
for a more detailed list. All control registers for the
channel must be rewritten after a Channel Reset
command.
Command4
(Enable Interrupt On Next RxCharac-
ter
).
ThiscommandisusedtoreactivatetheReceive
Interrupt On First Character Only interrupt mode.
This command is normally issued afterthe present
message iscompleted but before the next message
has started to be assembled. The next character to
enter the receive data FIFO after this command is
issued will cause a receiver interrupt request.
Note: Ifthe data FIFOhasmore than one character
stored when this command is issued, the first pre-
viously stored character will cause the receiver in-
terrupt request.
D5, D4, D3 : Command Codes
Command CMD2 CMD1 CMD0
0
0
1
2
3
4
5
6
7
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Null Command
(no effect)
Send Abort
(SDLC mode)
Reset External/
Status Interrupts
Channel Reset
Enable Interrupt On
Next Rx Character
Reset Tx Interrupt
Pending
Error Reset
Null Command
(no effect)
D7
D6
D5
SYNC
MODE
1
D4
SYNC
MODE
0
D3
STOP
BITS
1
D2
STOP
BITS 0
D1
D0
CLOCK
RATE
1
CLOCK
RATE
0
PARITY
E/O
PARITY
ON/OFF
Command 5
(Reset Tx Interrupt Pending
).
When
the Transmit Interrupt Enable modeis selected, the
transmitter requests an interrupt when the transmit
buffer becomes empty. In thosecases, where there
are no more characters to be sent (at the end of
message, for example), issuing this command re-
setsthepending transmitinterrupt and prevents any
further transmitter interrupt requests until the next
character has been loaded into the transmit buffer
or until CRC has been completely sent.
Command 6
(Error Reset). This command resets
the upper seven bits in StatusRegister 1. Anytime
a Special Receive Condition exists when Receive
Interrupt On First Character Only mode is selected,
the data with thespecial condition is held in the re-
ceivedata FIFO until this command is issued.
Command 7
(Null). The Null command has no ef-
fecton theMK68564SIO.
D2, D1 : Not Used
(read as zeros)
D0 :
Loop Mode
When this bit is set to a 1, the transmitter output is
connected to the receiver input and TxC is connec-
ted to thereceiver clock. RxC and RxDpins are not
used by the receiver ; theyare bypassed internally.
RxC may still be used as the baud rate generator
output in Loop Mode.
MODE CONTROL REGISTER (MODECTL)
TheModeControl Register contains controlbitsthat
affect both the receiver and the transmitter. This re-
gistermustbeinitializedbeforeloading theInterrupt,
Tx, and Rx Control Registers, and the Sync Word
Registers. This register is reset to ”00H” by a chan-
nel or hardwarereset.
D7, D6 : ClockRate 1 and 0
These bits specify the multiplier between the input
shift clock rates (TxC x RxC) and data rate. The
same multiplier is used for both the transmitter and
receiver, although the input clock rates may be dif-
ferent. In x16, x32, and x64 clock modes, therecei-
ver startbit detection logicis enabled ;therefore, for
Synchronous modes, the x1 clock rate must be
specified.Any clock ratemaybe specified for Asyn-
chronous mode ; however, if the x1 clock rate is se-
lected, synchronization between the receive data
and the receive clock must be accomplished exter-
nally.
MK68564
27/46
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