
PEB 2255
FALC-LH V1.3
Functional Description T1/J1
Data Sheet
131
2000-07
5.3.2
The transmit elastic store with a size of max. 2
×
1
9
3 bit (two frames) serves as a
temporary store for the PCM data to adapt the system clock (SCL
KX
) to the internally
generated clock for the transmit data, and to re-translate time slot structure used in the
system to that of the line side. Its optimal start position is initiated when programming the
transmit time slot offset values. A difference in the effective data rates of system side and
transmit side may lead to an overflow/underflow of the transmit memory: thus, errors in
data transmission to the remote end may occur. This error condition (transmit slip) is
reported to the microprocessor via interrupt status registers.
The received bit stream from pin
X
DI is optionally stored in the transmit elastic buffer.
The memory is organized as the receive elastic buffer. Programming of the transmit
buffer size is done by SIC1.
X
BS1/0 :
X
BS1/0
=
00 : bypass of the transmit elastic buffer
X
BS1/0
=
01 : one frame buffer or 1
9
3 bits
Maximum of wander amplitude (peak-to-peak): (1
U
I
=
6
48
ns )
System interface clocking rate:
8
.1
9
2 MHz:
Max. wander :
8
0
U
I in channel translation mode 0
Max. wander : 50
U
I in channel translation mode 1
System interface clocking rate: 1.5
44
MHz:
max. wander: 7
4 U
I
average delay after performing a slip:
9
6 bits
X
BS1/0
=
10 : two frame buffer or 3
8
6 bits
System interface clocking rate:
8
.1
9
2 MHz:
1
4
2
U
I in channel translation mode 0
7
8 U
I in channel translation mode 1
System interface clocking rate: 1.5
44
MHz:
max. wander: 126
U
I
average delay after performing a slip: 1
9
3 bits
X
BS1/0
=
11 : short buffer or
9
6 bits :
System interface clocking rate:
8
.1
9
2 MHz:
Max. wander : 2
8 U
I in channel translation mode 0
;
channel translation mode 1 not
supported
System interface clocking rate: 1.5
44
MHz:
max. wander: 3
8 U
I
average delay after performing a slip:
48
bits
Transmit Elastic Buffer (T1/J1)
The functions of the transmit buffer are:
Clock adaption between system clock (SCL
KX
) and internally generated transmit
route clock (
X
CL
K
).
Compensation of input wander and jitter.
Frame alignment between system frame and transmit route frame