
PEB 2255
FALC-LH V1.3
Operational Description E1
Data Sheet
15
8
2000-07
6
Operational Description E1
6.1
Operational Overview E1
The FALC
-LH in principle can be operated in two modes, which are either E1 mode or
T1/J1 mode.
The device is programmable via a microprocessor interface which enables byte or word
access to all control and status registers.
After reset the FALC
-LH must be initialized first. General guidelines for initialization are
described in sections
“Device Initialization in E1 Mode” on page 158
and
“Device
Initialization in T1/J1 Mode” on page 163
The status registers are read-only and are updated continuously. Normally, the
processor reads the status registers periodically to analyze the alarm status and
signaling data.
6.2
Device Reset E1
The FALC
-LH is forced to the reset state if a high signal is input on pin RES for a
minimum period of 20
μ
s. During reset the FALC
-LH needs an active clocks on pins
SCL
K
R, SCL
KX
,
X
TAL1 and
X
TAL3. All output stages except of CL
K
16M, CL
K
12M,
CL
K8
M, CL
KX
, FSC,
X
CL
K
and RCL
K
are in a high impedance state, all internal flip-
flops are reset and most of the control registers are initialized with default values.
SIgnals (for example RL1/2 receive line) should not be applied before the device is
powered up.
After reset the device is initialized to E1 operation.
6.3
Device Initialization in E1 Mode
After reset, the FALC
-LH is initialized for doubleframe format with register values listed
in the following table.
Table 39
Initial Values after Reset (E1)
Register
FMR0
FMR1
FMR2
SIC1
SIC2
SIC3
Reset Value
00
H
00
H
00
H
00
H
00
H
00
H
Meaning
NR
Z
coding, no alarm simulation
;X
L1/2 stay tristate
PCM 30 – doubleframe format,
4
.0
9
6 Mbit/s system data
rate, no AIS transmission to remote end, payload loop off.
8
.1
9
2-MHz system clocking rate, receive buffer 2 frames,
transmit buffer bypass, automatic freeze signaling