
PEB 2255
FALC-LH V1.3
Signaling Controller Operating Modes
Data Sheet
172
2000-07
8.3
Signaling Controller Functions
8.3.1
Shared Flags
The closing Flag of a previously transmitted frame simultaneously becomes the opening
Flag of the following frame if there is one to be transmitted. The Shared Flag feature is
enabled by setting bit SFLG in control register CCR1.
8.3.2
Preamble Transmission
If enabled via register CCR3, a programmable
8
-bit pattern (defined by register PRE) is
transmitted with a selectable number of repetitions after Interframe Timefill transmission
is stopped and a new frame is ready to be sent.
Z
ero bit insertion is disabled during preamble transmission. To guarantee correct
function the programmed preamble value should be different to the Receive Address
Byte values. Otherwise the preamble could be detected as valid address with shared
flags.
In BOM mode the MSB of the preamble should be reset in order to achieve a faster
synchronization at the BOM receiver. After the preamble has been sent, the transmitter
inserts one sync byte (FF
H
) automatically before sending the contents of the transmit
FIFO.
8.3.3
Transparent Transmission and Reception
When programmed in the extended transparent mode via the MODE register
(MDS2...0
=
111), the FALC
-LH performs fully transparent data reception without
HDLC framing, i.e. without
FLAG deletion
CRC checking
Bit-stuffing
In order to enable fully transparent data reception, bit MODE.HRAC has to be set and
FF
H
has to be written to RAH2.
Received data is always shifted into RFIFO.
Data transmission is always performed out of
X
FIFO by shifting the contents of
X
FIFO
directly into the outgoing data stream. Transmission is initiated by setting CMDR.
X
TF. A
sync byte FF
H
is automatically sent before the first byte of the
X
FIFO is transmitted.
8.3.4
If the extended transparent mode is selected, the FALC
-LH supports the continuous
transmission of the contents of the transmit FIFO.
Cyclic Transmission (fully transparent)