
PEB 2255
FALC-LH V1.3
Introduction
Data Sheet
1
9
2000-07
Frame Aligner
Frame alignment/synthesis for 20
48
kbit/s according to IT
U
-T G.70
4
(E1) and for
15
44
kbit/s according to IT
U
-T G.70
4
and JT G.70
4
(T1/J1)
Programmable frame formats :
E1: Doubleframe, CRC Multiframe (E1)
T1:
4
-Frame Multiframe (F
4
,FT), 12-Frame Multiframe (F12, D3/
4
), Extended
Superframe (F2
4
, ESF), Remote Switch Mode (F72, SLC
9
6)
Selectable conditions for recover/loss of frame alignment
CRC
4
to non-CRC
4
interworking of IT
U
-T G. 706 Annex B (E1)
Error checking via CRC
4
procedures according to IT
U
-T G. 706 (E1)
Error checking via CRC6 procedures according to IT
U
-T G. 706 and JT G.706 (T1/J1)
Performs synchronization in ESF format according to NTT requirements (J1)
Alarm and performance monitoring per second
16 bit counter for CRC-, framing errors, code violations, error monitoring via E bit and
SA6 bit (E1), errored blocks, PRBS bit errors
Insertion and extraction of alarm indication signals (AIS, Remote
Y
ellow Alarm, A
UX
P)
IDLE code insertion for selectable channels
8
.1
9
2 MHz/2.0
48
MHz (E1) or
8
.1
9
2 MHz/1.5
44
MHz (T1/J1) system clock frequency
Selectable 20
48
/
4
0
9
6 kbit/s backplane interface with programmable receive/transmit
timeslot offset
Programmable tristate function of
4
0
9
6 kbit/s output via RDO
Elastic store for receive and transmit route clock wander and jitter compensation
;
controlled slip capability and slip indication
Programmable elastic buffer size: 2 frames/1 frame/short buffer/bypass
Supports fractional E1 or T1 access
Flexible transparent modes
Programmable In-Band Loop Code detection and generation (TR62
4
11)
Channel loop back, line loop back or payload loop back capabilities (TR5
4
016)
Pseudo random bit sequence (PRBS) generator and monitor
Provides loop-timed mode
Clear channel capabilities (T1/J1)
Signaling Controller
HDLC controller
Bit stuffing, CRC check and generation, flag generation, flag and address recognition,
handling of bit oriented functions, programmable preamble
DL-channel protocol for ESF format according to ANSI T1.
4
03 or according to AT
&
T
TR5
4
016 (T1/J1)
DL-channel protocol for F72 (SLC
9
6) format
CAS controller with last look capability, enhanced CAS- register access and freeze
signaling indication
Robbed bit signaling capability (T1/J1)