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參數(shù)資料
| 型號(hào)： | PSB7280 |
| 廠商： | SIEMENS A G |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | Joint Audio Decoder-Encoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 文件頁(yè)數(shù)： | 127/190頁(yè) |
| 文件大?。?/td> | 2177K |
| 代理商： | PSB7280 |
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PSB 7280
Semiconductor Group
127
Data Sheet 1998-07-01
XMSB
Transmit MSB first
When XMSB = 0, the least significant bit of a byte in the transmit FIFO is the
bit first transmitted (normal mode in HDLC/serial data communication
protocols).
When XMSB = 1, the most significant bit of a byte in the transmit FIFO is the
first bit transmitted.
Channel Configuration Register 1 CCR1
Read/Write
Address 27
H
Bit 7
RCS0
Bit 0
CCR1
RSCO
RFDIS
XCS0
TSCO
XFDIS
RCS0
Receive Clock Shift 0
Together with RCS2 and RCS1 in TSAR, determines the clock shift relative
to the frame synchronization signal. A clock shift of 0...7 is programmable.
Receive Time-Slot Continuous
When RSCO is equal to one, the time-slot capacity (normally given by
register RCCR, between 1 and 256 bits) is “infinity”. This means that the
time-slot will be always “active” so that data can be permanently received if
RAC = 1.
If RFDIS = 0, and if the time-slot count logic has been reset (by issuing
RRES while RAC = 0), time-slot logic can start operation and thus “activate”
a time-slot only after the first frame sync pulse is detected (i.e. on FSC, RFS,
or TFS, whichever has been selected). The time-slot offset register
TSAR + bit RCS0 mark the instant when the “infinite” time-slot will be
activated after the first frame sync pulse has occurred. If RFDIS = 1,
reception can start immediately, without the necessity to wait for the first
frame sync pulse.
Receive Frame Sync Disregard
When RFDIS is ‘1’, the time-slot generation logic disregards frame syncs. In
particular, if RFDIS = 1, receive time-slot is immediately considered as
permanently “active”, and remains activated as long as this condition
prevails, independent of RSCO.
Transmit Clock Shift 0
Together with XCS2 and XCS1 in TSAX, determines the clock shift relative
to the frame synchronization signal. A clock shift of 0...7 is programmable.
RSCO
RFDIS
XCS0
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